ST7263BEX datasheet(113/186 Pages) STMICROELECTRONICS

113 / 186 page

ST7263Bxx

On-chip peripherals

Doc ID 7516 Rev 8

113/186

Setting the START bit while the BUSY bit is cleared causes the interface to switch to Master

mode (M/SL bit set) and generates a Start condition.

Once the Start condition is sent, the EVF and SB bits are set by hardware with an interrupt if

the ITE bit is set.

Then the master waits for a read of the SR1 register followed by a write in the DR register

with the Slave address byte, holding the SCL line low (see Figure 48 Transfer sequencing

EV5).

Slave address transmission

Then the slave address byte is sent to the SDA line via the internal shift register.

After completion of this transfer (and acknowledge from the slave if the ACK bit is set), the

EVF bit is set by hardware with interrupt generation if the ITE bit is set.

Then the master waits for a read of the SR1 register followed by a write in the CR register

(for example set PE bit), holding the SCL line low (see Figure 48 Transfer sequencing

EV6).

Next the master must enter Receiver or Transmitter mode.

Master receiver

Following the address transmission and after the SR1 and CR registers have been

accessed, the master receives bytes from the SDA line into the DR register via the internal

shift register. After each byte the interface generates in sequence:

●

Acknowledge pulse if the ACK bit is set

●

EVF and BTF bits are set by hardware with an interrupt if the ITE bit is set.

Then the interface waits for a read of the SR1 register followed by a read of the DR register,

holding the SCL line low (see Figure 48 Transfer sequencing EV7).

To close the communication: before reading the last byte from the DR register, set the STOP

bit to generate the Stop condition. The interface goes automatically back to slave mode

(M/SL bit cleared).

Note:

In order to generate the non-acknowledge pulse after the last received data byte, the ACK

bit must be cleared just before reading the second last data byte.

Master transmitter

Following the address transmission and after SR1 register has been read, the master sends

bytes from the DR register to the SDA line via the internal shift register.

The master waits for a read of the SR1 register followed by a write in the DR register,

holding the SCL line low (see Figure 48 Transfer sequencing EV8).

When the acknowledge bit is received, the interface sets, EVF and BTF bits with an interrupt

if the ITE bit is set.

To close the communication: after writing the last byte to the DR register, set the STOP bit to

generate the Stop condition. The interface goes automatically back to slave mode (M/SL bit

cleared).

Error cases

●

BERR: Detection of a Stop or a Start condition during a byte transfer. In this case, the

EVF and BERR bits are set by hardware with an interrupt if ITE is set.

Note that BERR will not be set if an error is detected during the first or second pulse of

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