MPC8378CVRALGA datasheet(54/126 Pages) FREESCALE

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MPC8378E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 2

Freescale Semiconductor

Enhanced Secure Digital Host Controller (eSDHC)

Figure 33 provides the eSDHC clock input timing diagram.

Figure 33. eSDHC Clock Input Timing Diagram

11.3.1

High-Speed Output Path (Write)

Figure 34 provides the data and command output timing diagram.

Figure 34. High Speed Output Path

11.3.1.1

High-Speed Write Meeting Setup (Maximum Delay)

The following equations show how to calculate the allowed skew range between the SD_CLK and

SD_DAT/CMD signals on the PCB.

Zero clock delay:

tSHSKHOV + tDATA_DELAY + tISU < tSHSCKL

With clock delay:

tSHSKHOV + tDATA_DELAY + tISU < tSHSCKL + tCLK_DELAY

tDATA_DELAY – tCLK_DELAY < tSHSCKL – tISU – tSHSKHOV

eSDHC

tSHSCKR

External Clock

tSHSCK

tSHSCKF

VM = Midpoint Voltage (OVDD/2)

operational mode

tSHSCKL

tSHSCKH

Output Valid Time: tSHSKHOV

Output Hold Time: tSHSKHOX

tIH (2 ns)

tCLK_DELAY

Input at the

SD CLK at

Driving

Edge

Sampling

Edge

the Card Pin

SD Card Pins

tISU (6 ns)

tDATA_DELAY

tSHSCKL

tSHSCK (Clock Cycle)

SD CLK at the

MPC8378E Pin

Output from the

MPC8378E Pins

MPC8378CVRALGA 数据表(PDF) 54 Page - Freescale Semiconductor, Inc

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