MPC8378CVRALGA datasheet(88/126 Pages) FREESCALE

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MPC8378E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 2

Freescale Semiconductor

Package and Pin Listings

20.3

SerDes Transmitter and Receiver Reference Circuits

Figure 65 shows the reference circuits for SerDes data lane’s transmitter and receiver.

Figure 65. SerDes Transmitter and Receiver Reference Circuits

The DC and AC specification of SerDes data lanes are defined in each interface protocol section below in

this document based on the application usage:

•

Section 8, “Ethernet: Enhanced Three-Speed Ethernet (eTSEC)”

•

Section 15, “PCI Express”

Note that an external AC coupling capacitor is required for the above three serial transmission protocols

with the capacitor value defined in specification of each protocol section.

21 Package and Pin Listings

This section details package parameters, pin assignments, and dimensions.

21.1

Package Parameters for the MPC8378E TePBGA II

The package parameters are provided in the following list. The package type is 31 mm

× 31 mm,

689 plastic ball grid array (TePBGA II).

Package outline

31 mm

× 31 mm

Interconnects

689

Pitch

1.00 mm

Module height (typical)

2.0 mm to 2.46 mm (maximum)

Solder Balls

3.5% Ag, 96.5% Sn

Ball diameter (typical)

0.60 mm

Receiver

Transmitter

SD1_TX

n or

SD2_TX

SD1_TX

n or

SD2_TX

SD1_RX

n or

SD2_RX

SD1_RX

n or

SD2_RX

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