MPC8378CVRALGA datasheet(85/126 Pages) FREESCALE

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MPC8378E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 2

Freescale Semiconductor

High-Speed Serial Interfaces (HSSI)

that the LVPECL clock driver’s output impedance is 50

Ω. R1 is used to DC-bias the LVPECL outputs

prior to AC-coupling. Its value could be ranged from 140

Ω to 240 Ω depending on clock driver vendor’s

requirement. R2 is used together with the SerDes reference clock receiver’s 50

Ω termination resistor to

attenuate the LVPECL output’s differential peak level such that it meets the device SerDes reference

clock’s differential input amplitude requirement (between 200 mV and 800 mV differential peak). For

example, if the LVPECL output’s differential peak is 900 mV and the desired SerDes reference clock input

amplitude is selected as 600 mV, the attenuation factor is 0.67, which requires R2 = 25

Ω. Please consult

clock driver chip manufacturer to verify whether this connection scheme is compatible with a particular

clock driver chip.

Figure 61. AC-Coupled Differential Connection with LVPECL Clock Driver (Reference Only)

n_REF_CLK

Clock Driver

100

Ω differential PWB trace

SerDes Refer.

CLK Receiver

Clock Driver

CLK_Out

LVPECL CLK Driver Chip

10 nF

MPC8378E

MPC8378CVRALGA 数据表(PDF) 85 Page - Freescale Semiconductor, Inc