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SC9S12HY64J0CLHR 数据表(PDF) 59 Page - Freescale Semiconductor, Inc

部件名 SC9S12HY64J0CLHR
功能描述  S12 Microcontrollers
PDF  790 Pages
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制造商  FREESCALE [Freescale Semiconductor, Inc]
网页  http://www.freescale.com
标志 FREESCALE - Freescale Semiconductor, Inc

SC9S12HY64J0CLHR 数据表(HTML) 59 Page - Freescale Semiconductor, Inc

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Port Integration Module (S12HYPIMV1)
MC9S12HY/HA-Family Reference Manual, Rev. 1.04
Freescale Semiconductor
59
2.3
Memory Map and Register Definition
This section provides a detailed description of all Port Integration Module registers.
V
PV[7]
M3C1P
O
Motor control output for motor 3
GPIO
GPIO
I/O General purpose
PV[6]
M3C1M
O
Motor control output for motor 3
IOC1_3
I/O TIM1 channel 3
GPIO
I/O General purpose
PV[5]
M3C0P
O
Motor control output for motor 3
GPIO
I/O General purpose
PV[4]
M3C0M
O
Motor control output for motor 3
IOC1_2
I/O TIM1 channel 2
GPIO
I/O General purpose
PV3
M2C1P
O
Motor control output for Motor 2
SDA
I/O SDA of IIC, mappable through software
PWM7
I/O PWM channel 7, mappable through software
SS
I/O SS of SPI, mappable through software
GPIO
I/O General purpose
PV2
M2C1M
O
Motor control output for Motor 2
IOC1_1
I/O TIM1 channel 1
SCK
I/O SCK of SPI, mappable through software
PWM6
I/O PWM channel 6, mappable through software
GPIO
I/O General purpose
PV1
M2C0P
O
Motor control output for Motor 2
MOSI
I/O MOSI of SPI, mappable through software
PWM5
O
PWM channel 5, mappable through software
GPIO
I/O General purpose
PV0
M2C0M
O
Motor control output for Motor 2
IOC1_0
I/O TIM1 channel 0
SCL
I/O SCL of IIC, mappable through software
PWM4
O
PWM channel 4, mappable through software
MISO
I/O MISO of SPI, mappable through software
GPIO
I/O General purpose
1 Signals in brackets denote alternative module routing pins.
2 Function active when RESET asserted.
Port
Pin Name
Pin Function
& Priority1
I/O
Description
Pin Function
after Reset



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