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SC9S12HY64J0CLHR 数据表(PDF) 60 Page - Freescale Semiconductor, Inc |
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SC9S12HY64J0CLHR 数据表(HTML) 60 Page - Freescale Semiconductor, Inc |
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60 / 790 page  Port Integration Module (S12HYPIMV1) MC9S12HY/HA-Family Reference Manual, Rev. 1.04 60 Freescale Semiconductor 2.3.1 Memory Map Table 2-2 shows the register map of the Port Integration Module. Table 2-2. Block Memory Map Port Offset or Address Register Access Reset Value Section/Page A B 0x0000 PORTA—Port A Data Register R/W 0x00 2.3.3/2-71 0x0001 PORTB—Port B Data Register R/W 0x00 2.3.4/2-72 0x0002 DDRA—Port A Data Direction Register R/W 0x00 2.3.5/2-72 0x0003 DDRB—Port B Data Direction Register R/W 0x00 2.3.6/2-73 0x0004 : : 0x0009 PIM Reserved R 0x00 2.3.7/2-74 0x000A : 0x000B Non-PIM address range1 - - - A B 0x000C PUCR—Pull-up Up Control Register R/W2 0x43 2.3.8/2-74 0x000D RDRIV—Reduced Drive Register R/W 0x00 2.3.9/2-75 0x000E : 0x001B Non-PIM address range1 - - - 0x001C ECLKCTL—ECLK Control Register R/W 0x80 2.3.10/2-77 0x001D PIM Reserved R 0x00 2.3.11/2-77 0x001E IRQCR—IRQ Control Register R/W2 0x00 2.3.12/2-78 0x001F PIM Reserved R 0x00 2.3.13/2-78 0x0020 : 0x023F Non-PIM address range1 - - - T 0x0240 PTT—Port T Data Register R/W 0x00 2.3.14/2-79 0x0241 PTIT—Port T Input Register R 3 2.3.15/2-80 0x0242 DDRT—Port T Data Direction Register R/W 0x00 2.3.16/2-81 0x0243 RDRT—Port T Reduced Drive Register R/W 0x00 2.3.17/2-81 0x0244 PERT—Port T Pull Device Enable Register R/W 0xFF 2.3.18/2-82 0x0245 PPST—Port T Polarity Select Register R/W 0xFF 2.3.19/2-82 0x0246 PIM Reserved R 0x00 2.3.20/2-83 0x0247 PTTRR Port T Routing Register R/W 0x00 2.3.21/2-83 |
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