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SC9S12HY64J0CLHR 数据表(PDF) 82 Page - Freescale Semiconductor, Inc |
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SC9S12HY64J0CLHR 数据表(HTML) 82 Page - Freescale Semiconductor, Inc |
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82 / 790 page  Port Integration Module (S12HYPIMV1) MC9S12HY/HA-Family Reference Manual, Rev. 1.04 82 Freescale Semiconductor 2.3.18 Port T Pull Device Enable Register (PERT) 2.3.19 Port T Polarity Select Register (PPST) 1 Read: Anytime Write: Anytime Table 2-15. RDRT Register Field Descriptions Field Description 7-0 RDRT Port T reduced drive—Select reduced drive for output pin This bit configures the drive strength of the associated output pin as either full or reduced. If a pin is used as input this bit has no effect. The reduced drive function is independent of which function is being used on a particular pin. 1 Reduced drive selected (1/6 of the full drive strength) 0 Full drive strength enabled Address 0x0244 Access: User read/write1 1 Read: Anytime Write: Anytime 76543210 R PERT7 PERT6 PERT5 PERT4 PERT3 PERT2 PERT1 PERT0 W Reset 11111111 Figure 2-16. Port T Pull Device Enable Register (PERT) Table 2-16. PERT Register Field Descriptions Field Description 7-0 PERT Port T pull device enable—Enable pull device on input pin This bit controls whether a pull device on the associated port input pin is active. If a pin is used as output this bit has no effect. The polarity is selected by the related polarity select register bit. 1 Pull device enabled 0 Pull device disabled Address 0x0245 Access: User read/write1 1 Read: Anytime Write: Anytime 76543210 R PPST7 PPST6 PPST5 PPST4 PPST3 PPST2 PPST1 PPST0 W Reset 11111111 Figure 2-17. Port T Polarity Select Register (PPST) |
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