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SC9S12HY64J0CLHR 数据表(PDF) 70 Page - Freescale Semiconductor, Inc

部件名 SC9S12HY64J0CLHR
功能描述  S12 Microcontrollers
PDF  790 Pages
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制造商  FREESCALE [Freescale Semiconductor, Inc]
网页  http://www.freescale.com
标志 FREESCALE - Freescale Semiconductor, Inc

SC9S12HY64J0CLHR 数据表(HTML) 70 Page - Freescale Semiconductor, Inc

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Port Integration Module (S12HYPIMV1)
MC9S12HY/HA-Family Reference Manual, Rev. 1.04
70
Freescale Semiconductor
Table 2-3. Pin Configuration Summary
NOTE
All register bits in this module are completely synchronous to internal
clocks during a register read.
NOTE
Figure of port data registers also display the alternative functions if
applicable on the related pin as defined in Table 2-1. Names in brackets
denote the availability of the function when using a specific routing option.
NOTE
Figures of module routing registers also display the module instance or
module channel associated with the related routing bit.
DDR
IO
RDR
PE
PS1
1 Always “1” on Port A, B, and always “0” on AD.
IE2
2 Applicable only on Port T, S, R and AD.
Function
Pull Device
Interrupt
0
x
x
0
x
0
Input
Disabled
Disabled
0
x
x
1
0
0
Input
Pull Up
Disabled
0
x
x
1
1
0
Input
Pull Down
Disabled
0
x
x
0
0
1
Input
Disabled
Falling edge
0
x
x
0
1
1
Input
Disabled
Rising edge
0
x
x
1
0
1
Input
Pull Up
Falling edge
0
x
x
1
1
1
Input
Pull Down
Rising edge
1
0
0
x
x
0
Output, full drive to 0
Disabled
Disabled
1
1
0
x
x
0
Output, full drive to 1
Disabled
Disabled
1
0
1
x
x
0
Output, reduced drive to 0
Disabled
Disabled
1
1
1
x
x
0
Output, reduced drive to 1
Disabled
Disabled
1
0
0
x
0
1
Output, full drive to 0
Disabled
Falling edge
1
1
0
x
1
1
Output, full drive to 1
Disabled
Rising edge
1
0
1
x
0
1
Output, reduced drive to 0
Disabled
Falling edge
1
1
1
x
1
1
Output, reduced drive to 1
Disabled
Rising edge



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