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数据搜索系统，热门电子元器件搜索 |
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SC9S12HY64J0CLHR 数据表(PDF) 83 Page - Freescale Semiconductor, Inc |
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SC9S12HY64J0CLHR 数据表(HTML) 83 Page - Freescale Semiconductor, Inc |
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83 / 790 page  Port Integration Module (S12HYPIMV1) MC9S12HY/HA-Family Reference Manual, Rev. 1.04 Freescale Semiconductor 83 2.3.20 PIM Reserved Register 2.3.21 Port T Routing Register (PTTRR) This register configures the re-routing of TIM0/1 channels on alternative pins on Port R/T. Table 2-17. PPST Register Field Descriptions Field Description 7-0 PPST Port T pull device select—Configure pull device polarity on input pin This bit selects a pull-up or a pull-down device if enabled on the associated port input pin. 1 A pull-down device is selected 0 A pull-up device is selected Address 0x0246 Access: User read1 1 Read: Always reads 0x00 Write: Unimplemented 76543210 R 00000000 W Reset 00000000 = Unimplemented or Reserved Figure 2-18. PIM Reserved Register Address 0x0247 Access: User read1 1 Read: Anytime Write: Anytime 76543210 R0 0 PTTRR5 PTTRR4 00 PTTRR1 PTTRR0 W Routing Option — — IOC0_7 IOC0_6 — — IOC1_7 IOC1_6 Reset 00000000 = Unimplemented or Reserved Figure 2-19. Port T Routing Register (PTTRR) |
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