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SC9S12HY64J0CLHR 数据表(PDF) 84 Page - Freescale Semiconductor, Inc |
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SC9S12HY64J0CLHR 数据表(HTML) 84 Page - Freescale Semiconductor, Inc |
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84 / 790 page  Port Integration Module (S12HYPIMV1) MC9S12HY/HA-Family Reference Manual, Rev. 1.04 84 Freescale Semiconductor 2.3.22 Port S Data Register (PTS) Table 2-18. Port T Routing Register Field Descriptions Field Description 5 PTTRR Port T data direction— This register controls the routing of IOC0_7. 0 IOC0_7 routed to PT7 1 IOC0_7 routed to PR1 4 PTTRR Port T data direction— This register controls the routing of IOC0_6. 0 IOC0_6 routed to PT6 1 IOC0_6 routed to PR0 1 PTTRR Port T data direction— This register controls the routing of IOC1_7. 0 IOC1_7routed to PT3 1 IOC1_7 routed to PR3 0 PTTRR Port T data direction— This register controls the routing of IOC1_6. 0 IOC1_6 routed to PT2 1 IOC1_6 routed to PR2 Address 0x0248 Access: User read/write1 1 Read: Anytime The data source is depending on the data direction value. Write: Anytime 76543210 R PTS7 PTS6 PTS5 PTS4 PTS3 PTS2 PTS1 PTS0 W PWM3 PWM2 PWM1 PWM0 — — PWM7 PWM6 SDA —— SCL ———— Altern. Function SS SCK MOSI MISO TXCAN RXCAN TXD RXD Reset 00000000 Figure 2-20. Port S Data Register (PTS) |
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