HT83F40P datasheet(15/61 Pages) HOLTEK

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HT83FXX

Rev. 1.00

May 12, 2009

Voice Control and Audio output Registers

DAL, DAH, VOL

The devices include a single 12-bit current type DAC

function for driving an external 8

W speaker through an

external NPN transistor or Power Amplifier. The pro-

grammer must writer the voice data to these DAL/DAH

registers. The programmer can control the DAC volume

with 7-levels via the VOL register.

Pulse Width Modulator Registers

PWMC, PWML, PWMH

Each device contains a single 12-bit PWM function for

driving an external 8

W speaker. The programmer must

writer the voice data to PWML/PWMH register. The pro-

grammer can control the PWM volume with 8-levels via

the VOL register.

Serial Interface Module(SIM) Registers

SIMC0, SIMC1, SIMAR/SIMC2, SIMDR

Each SIM contains SPI and I

2C function for communi-

cating with other microcontroller or SPI Flash Memory.

All devices contain an integrated I

2C and SPI bus which

interfaces to the external shared pins SDA ,SCL and

SCSB ,SCK ,SDI ,SDO with PB on the microcontroller.

The I

2C correct setup and data transfer operation of this

2-line bidirectional bus utilizes 4 special function regis-

ters. The SIMAR register sets the slave address of the

device while the SIMC0 is the control register that en-

ables or disables the device as well as select whether it

is in I

2C or SPI mode. The SIMC1 register is the I2C sta-

tus register while the SIMDR register is the input/output

data register. The SPI correct setup and data transfer

operation of this 3-line bidirectional bus utilizes 3 special

function registers. The SIMC0 is the control register that

enables or disables the device as well as select whether

it is in I

2C or SPI mode. The SIMC2 register is the SPI

status register while the SIMDR register is the input/out-

put data register.

Flash Data Memory

The Data Memory is the location where the user Data is

stored. For this device the Data Memory is a Flash type,

which means it can be programmed and reprogrammed

a large number of times, allowing the user the conve-

nience of voice data modification using the same de-

vice. By using the appropriate programming tools, these

devices offer users the flexibility to conveniently change

and develop their applications while also offering a

means of field programming.

Flash Data Memory Structure

The internal Flash Data Memory has a capacity of be-

tween 2M

´8 bit and 128K´8 bit. Unlike the Program

Memory and RAM Data Memory, the Flash Data Memory

is not directly mapped and is therefore not directly acces-

sible in the same way as the other types of memory.

Accessing the Flash Data Memory

The Flash Data Memory is accessed using a set of

Macros in the library. These instructions control all func-

tions of the Flash such as read, write, erase, enable etc.

The internal Flash structure is similar to that of a stan-

dard SPI Flash Memory, for which 4 pins are used for

transfer of instruction, address and data information.

These are the Chip Select pin, CS, Serial Clock pin,

SCK, Data In pin, SI and the Data Out pin, SO. All ac-

tions related to the Flash Memory must be conducted

through each of these four Flash Memory download

pins. By manipulating these four pin in the device, in ac-

cordance with the accompanying timing diagrams, the

microcontroller can communicate with the Flash Mem-

ory and carry out the required read and write instruc-

tions.

When reading data from the Flash Memory, CS should

be set to

²0² to start the data transmission. The data will

clocked out on the rising edge of SCK and appear on

SO. The SO pin will normally be in a high-impedance

condition unless a READ statement is being executed.

When writing to the Flash Memory the data must be pre-

sented first on SI and then clocked in on the rising edge

of SCK. After all the instruction, address and data infor-

mation has been transmitted, CS should be set to

²1² to

terminate the data transmission. Note that after power

on the Flash Memory must be initialised as described.

READ

The

²READ² instruction is used to read out one or more

bytes of data from the Flash Data Memory. To instigate a

²READ² instruction, the CS bit should be set low, fol-

lowed by a command instruction and then the instruction

code

²03², all transmitted via the SI bit. The address in-

formation should then follow with the MSB being trans-

mitted first. After the last address bit, A0, has been

transmitted, the data can be clocked out, bit D7 first, on

the rising edge of the SCK clock signal and can be read

via the SO bit. The data information will first precede the

reading of the first data bit, D7. After the full byte has

been read out, the internal address will be automatically

incremented allowing the next consecutive data byte to

be read out without entering further address data. As

long as the CS bit remains low, data bit D7 of the next

address will automatically follow data bit D0 of the previ-

ous address being inserted between them. The address

will keep incrementing in this way until CS returns to a

high value. SO will normally be in a high impedance con-

dition until the

²READ² instruction is executed.

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