HT83F40P datasheet(29/61 Pages) HOLTEK

29 / 61 page

HT83FXX

Rev. 1.00

May 12, 2009

The following gives further explanation of each bit:

¨ SIMEN

The SIMEN bit determines if the I

2C bus is enabled

or disabled. If data is to be transferred or received

on the I

2C bus then this bit must be set high.

The following gives further explanation of each bit:

¨ HCF

The HCF flag is the data transfer flag. This flag will

be zero when data is being transferred. Upon com-

pletion of an 8-bit data transfer the flag will go high

and an interrupt will be generated.

¨ HASS

The HASS flag is the address match flag. This flag

is used to determine if the slave device address is

the same as the master transmit address. If the ad-

dresses match then this bit will be high, if there is no

match then the flag will be low.

¨ HBB

The HBB flag is the I

2C busy flag. This flag will be

high when the I

2C bus is busy which will occur when

a START signal is detected. The flag will be reset to

zero when the bus is free which will occur when a

STOP signal is detected.

¨ HTX

The HTX flag is the transmit/receive mode bit. This

flag should be set high to set the transmit mode and

low for the receive mode.

¨ TXAK

The TXAK flag is the transmit acknowledge flag. Af-

ter the receipt of 8-bits of data, this bit will be trans-

mitted to the bus on the 9th clock. To continue

receiving more data, this bit has to be reset to zero

before further data is received.

¨ SRW

The SRW bit is the Slave Read/Write bit. This bit de-

termines whether the master device wishes to

transmit or receive data from the I

2C bus. When the

transmitted address and slave address match, that

is when the HAAS bit is set high, the device will

check the SRW bit to determine whether it should

be in transmit mode or receive mode. If the SRW bit

is high, the master is requesting to read data from

the bus, so the device should be in transmit mode.

When the SRW bit is zero, the master will write data

to the bus, therefore the device should be in receive

mode to read this data.

¨ RNIC

The RNIC bit is used as I

2C running clock from Inter-

nal or external clock. If this bit is low then I

2C run-

ning using internal clock and it will not wake-up

when I

2C interrupts in the Power Down Mode. If the

bit is high I

2C running using external clock and it will

wake-up when I

2C interrupts in the Power Down

Mode.

¨ RXAK

The RXAK flag is the receive acknowledge flag.

When the RXAK bit has been reset to zero it means

that a correct acknowledge signal has been re-

ceived at the 9th clock, after 8 bits of data have

been transmitted. When in the transmit mode, the

transmitter checks the RXAK bit to determine if the

receiver wishes to receive the next byte. The trans-

mitter will therefore continue sending out data until

the RXAK bit is set to

²1². When this occurs, the

transmitter will release the SDA line to allow the

master to send a STOP signal to release the bus.

S I M C 1 R e g i s t e r

b 7

R e c e i v e a c k n o w l e d g e f l a g

1 : n o t a c k n o w l e d g e d

0 : a c k n o w l e d g e d

I 2 C r u n i n g c l o c k

1 : I 2 C r u n i n g i s n o t u s i n g i n t e r n a l c l o c k

0 : I 2 C r u n i n g i s u s i n g i n t e r n a l c l o c k

M a s t e r d a t a r e a d / w r i t e r e q u e s t f l a g

1 : r e q u e s t d a t a r e a d

0 : r e q u e s t d a t a w r i t e

T r a n s m i t a c k n o w l e d g e f l a g

1 : d o n ' t a c k n o w l e d g e

0 : a c k n o w l e d g e

T r a n s m i t / R e c e i v e m o d e

1 : t r a n s m i t m o d e

0 : r e c e i v e m o d e

I 2 C b u s b u s f l a g

1 : b u s y

0 : n o t b u s y

C a l l i n g a d d r e s s m a t c h e d f l a g

1 : m a t c h e d

0 : n o t m a t c h e d

D a t a t r a n s f e r f l a g

1 : t r a n s f e r c o m p l e t e

0 : t r a n s f e r n o t c o m p l e t e

b 0

H T X

R X A K

S R W

T X A K

H B B

H A A S

H C F

R N I C

2C Control Register

- SIMC1

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