HT83F40P datasheet(33/61 Pages) HOLTEK

33 / 61 page

HT83FXX

Rev. 1.00

May 12, 2009

Interrupts

Interrupts are an important part of any microcontroller

system. When an internal function such as a Time Base

or Timer requires microcontroller attention, their corre-

sponding interrupt will enforce a temporary suspension

of the main program allowing the microcontroller to di-

rect attention to their respective needs. Each device

contains a Time Base interrupt and two internal timer in-

terrupt functions. The Time Base interrupt is controlled

by bit 1 of INTC register, while the internal interrupt is

controlled by the Timer Counter overflow.

Interrupt Register

Overall interrupt control, which means interrupt enabling

and flag setting, is controlled using two registers, known

as INTC and INTCH, which are located in the Data

Memory. By controlling the appropriate enable bits in

these registers each individual interrupt can be enabled

or disabled. Also when an interrupt occurs, the corre-

sponding request flag will be set by the microcontroller.

The global enable flag if cleared to zero will disable all

interrupts.

Interrupt Operation

A timer or Time Base overflow or by setting their corre-

sponding request flag, if their appropriate interrupt en-

able bit is set. When this happens, the Program

Counter, which stores the address of the next instruction

to be executed, will be transferred onto the stack. The

Program Counter will then be loaded with a new ad-

dress which will be the value of the corresponding inter-

rupt vector. The microcontroller will then fetch its next

instruction from this interrupt vector. The instruction at

this vector will usually be a JMP statement which will

take program execution to another section of program

which is known as the interrupt service routine. Here is

located the code to control the appropriate interrupt. The

interrupt service routine must be terminated with a RETI

statement, which retrieves the original Program Counter

address from the stack and allows the microcontroller to

continue with normal execution at the point where the in-

terrupt occurred.

The various interrupt enable bits, together with their as-

sociated request flags, are shown in the accompanying

diagram with their order of priority.

Once an interrupt subroutine is serviced, all the other in-

terrupts will be blocked, as the EMI bit will be cleared au-

tomatically. This will prevent any further interrupt nesting

from occurring. However, if other interrupt requests oc-

cur during this interval, although the interrupt will not be

immediately serviced, the request flag will still be re-

corded. If an interrupt requires immediate servicing

while the program is already in another interrupt service

routine, the EMI bit should be set after entering the rou-

tine, to allow interrupt nesting. If the stack is full, the in-

terrupt request will not be acknowledged, even if the

related interrupt is enabled, until the Stack Pointer is

decremented. If immediate service is desired, the stack

must be prevented from becoming full.

I N T C R e g i s t e r

b 7

b 0

E T 0

E T B I E M I

T B F

T 0 F

E T 1

T 1 F

M a s t e r I n t e r r u p t G l o b a l E n a b l e

1 : g l o b a l e n a b l e

0 : g l o b a l d i s a b l e

T i m e B a s e I n t e r r u p t E n a b l e

1 : e n a b l e

0 : d i s a b l e

T i m e r 0 I n t e r r u p t E n a b l e

1 : e n a b l e

0 : d i s a b l e

T i m e r 1 I n t e r r u p t E n a b l e

1 : e n a b l e

0 : d i s a b l e

T i m e B a s e I n t e r r u p t R e q u e s t F l a g

1 : a c t i v e

0 : i n a c t i v e

T i m e r 0 I n t e r r u p t R e q u e s t F l a g

1 : a c t i v e

0 : i n a c t i v e

T i m e r 1 I n t e r r u p t R e q u e s t F l a g

1 : a c t i v e

0 : i n a c t i v e

N o i m p l e m e n t e d , r e a d a s " 0 "

Interrupt Control Register

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