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ST7713 数据表(PDF) 56 Page - Sitronix Technology Co., Ltd. |
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ST7713 数据表(HTML) 56 Page - Sitronix Technology Co., Ltd. |
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56 / 159 page  ST7713 Ver 1.6 2008-05 56 Table 9.9.1 Rules for updating order Condition Horizontal Counter Vertical Counter An active VS signal is received Return to 0 Return to 0 Signal pixel information of the active area is received Increment by 1 No change An active HS signal between two active area lines Return to 0 Increment by 1 The horizontal counter is larger than 239 and the vertical counter is larger than 319 Return to 0 Return to 0 Note 1. Pixel order is RGB on the display. Note 2. Data streaming direction from the host to the display is described in the following figure. Fig. 9.9.3 Data streaming order for RGB interface 9.9.4 RGB Interface Bus Width set All 4-kinds of bus width can be available in RGB interface mode (selected by COLMOD (3Ah) command for 6-bit, 16-bit and 18-bit data width) VIPF[3:0] D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Bus width 0101 R4 R3 R2 R1 R0 x G5 G4 G3 G2 G1 G0 B4 B3 B2 B1 B0 x 16-bit data 0110 R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 18-bit data x x x x x x x x x x X x R5 R4 R3 R2 R1 R0 x x x x x x x x x x X X G5 G4 G3 G2 G1 G0 1110 x x x x x x x x x x x X B5 B4 B3 B2 B1 B0 6-bit data Note 1: When VIPF[3:0]=”1110”, 6-bit data width of 3-times transfer is used to transmit 1 pixel data with the 18-bit color depth information. Note 2: Only VIPF[3:0]= ”0101” , “0110” and “1110” are valid on RGB I/F, Others are invalid. Note 3. ‘x’ Don’t care, but need to set VDDI or DGND level. 9.9.5 RGB Interface Mode Set Table 9.9.5.1 RGB Interface Mode Setting RGB I/F Mode PCLK DE VS HS Video Data bus D[17:0] Register for Blanking Porch setting Reference clock for Display RGB Mode 1 Used Used Used Used Used Not Used Internal Oscillator RGB Mode 2 Used Used Used Used Used Used Internal Oscillator There are 2-kinds of RGB mode which is selected by RCM1 & RCM0 hardware pins. In RGB Mode 1 (RCM1, RCM0 = “10”), writing data to frame memory is done by PCLK and data bus (D[17:0]), when DE is in high state. The external synchronization signals (PCLK, VS and HS) are used for internal display signals. So, controller (host) must always transfer PCLK, VS, HS and DE signals to driver. In RGB Mode 2 (RCM1, RCM0 = “11”), blanking porch setting of VS and HS signals are defined by RGBBPCTR (B5h) command. DE pin is used for data making. When DE pin is high, valid data is directly stored to frame memory. In the contrast, if DE pin is low the data of frame memory will keep same status. |
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