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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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WM9704CFT/V 数据表(PDF) 8 Page - Wolfson Microelectronics plc |
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WM9704CFT/V 数据表(HTML) 8 Page - Wolfson Microelectronics plc |
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8 / 35 page  WM9704Q Production Data WOLFSON MICROELECTRONICS LTD PD Rev 2.3 January 2001 8 WARM RESET SYNC BIT_CLK t SYNC_HIGH t SYNC2CLK Figure 3 Warm Reset Timing PARAMETER SYMBOL MIN TYP MAX UNIT SYNC active high pulse width tSYNC_HIGH 1.3 µs SYNC inactive to BIT_CLK startup delay tSYNC2_CLK 162.4 ns CLOCK SPECIFICATIONS BIT_CLK SYNC t CLK_HIGH t CLK_LOW t CLK_PERIOD t SYNC_HIGH t SYNC_LOW t SYNC_PERIOD Figure 4 Clock Specifications (50pF External Load) PARAMETER SYMBOL MIN TYP MAX UNIT BIT_CLK frequency 12.288 MHz BIT_CLK period tCLK_PERIOD 81.4 ns BIT_CLK output jitter 750 ps BIT_CLK high pulse width (Note 1) tCLK_HIGH 32.56 40.7 48.84 ns BIT_CLK low pulse width (Note 1) tCLK_LOW 32.56 40.7 48.84 ns SYNC frequency 48.0 KHz SYNC period tSYNC_PERIOD 20.8 µs SYNC high pulse width tSYNC_HIGH 1.3 µs SYNC low pulse width tSYNC_LOW 19.5 µs Note: Worst case duty cycle restricted to 40/60 |
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