Production Data

WM9704Q

WOLFSON MICROELECTRONICS LTD

PD Rev 2.3 January 2001

23

SLOT 3: PCM RECORD LEFT CHANNEL

Audio input frame slot 3 is the left channel output of the WM9704Q’s input Mux, post-ADC.

The WM9704Q’s ADCs can be implemented to support 16, 18, or 20-bit resolution. The WM9704Q

ships out its ADC output data (MSB first), and stuffs any trailing non-valid bit positions with 0s to fill

out its 20-bit time slot.

SLOT 4: PCM RECORD RIGHT CHANNEL

Audio input frame slot 4 is the right channel output of the WM9704Q’s input Mux, post-ADC.

The WM9704Q’s ADCs can be implemented to support 16, 18, or 20-bit resolution.

The WM9704Q ships out its ADC output data (MSB first), and stuffs any trailing non-valid bit

positions with 0s to fill out its 20-bit time slot.

SLOT 5: OPTIONAL MODEM LINE 1 CODEC

Slot 5 is not supported.

SLOT 10: OPTIONAL MODEM LINE 2 CODEC

Slot 10 is not supported.

SLOT 6: OPTIONAL DEDICATED MICROPHONE RECORD DATA

Audio input frame slot 6 is an optional (post-ADC) third PCM system, input channel available for

dedicated use by a desktop microphone. This optional AC’97 feature is not supported by the

WM9704Q. This may be determined by the AC’97 controller interrogating the WM9704Q Vendor ID

register.

SLOTS 7 TO 11: RESERVED

Audio input frame slots 7 to 11 are reserved for future use and are always stuffed with 0s by AC ‘97.

SLOT 12:

GPIO functions supported.

AC-LINK LOW POWER MODE

The AC-link signals can be placed in a low power mode. When the WM9704Q’s powerdown Register

26h, is programmed to the appropriate value, both BIT_CLK and SDATA_IN will be brought to, and

held at a logic low voltage level.

BIT_CLK and SDATA_IN are transitioned low immediately following the decode of the write to the

Powerdown Register (26h) with PR4. When the AC’97 controller driver is at the point where it is

ready to program the AC-link into its low power mode, slots 1 and 2 are assumed to be the only valid

stream in the audio output frame. At this point in time it is assumed that all sources of audio input

have also been neutralised.

The AC’97 controller should also drive SYNC and SDATA_OUT low after programming the

WM9704Q to this low power, halted mode.

Once the WM9704Q has been instructed to halt BIT_CLK, a special wake up protocol must be used

to bring the AC-link to the active mode since normal audio output and input frames can not be

communicated in the absence of BIT_CLK.

WAKING UP THE AC-LINK

There are 2 methods for bringing the AC-link out of a low power, halted mode. Regardless of the

method, it is the AC’97 controller that performs the wake up task.

AC-link protocol provides for a Cold WM9704Q Reset, and a Warm WM9704Q Reset.

The current powerdown state would ultimately dictate which form of WM9704Q reset is appropriate.

Unless a cold or register reset (a write to the reset register) is performed, wherein the WM9704Q

registers are initialised to their default values, registers are required to keep state during all

powerdown modes.