Production Data

WM9704Q

WOLFSON MICROELECTRONICS LTD

PD Rev 2.3 January 2001

13

REVISION 2.1 COMPLIANT 2-CHANNEL MODE

Features in this mode are as follows:

•

Vendor ID reads back as WML3.

•

2 channels of ADC and DAC conversion provided, with all recommended audio and modem

sample rates supported via the audio sample rate registers 2Ch and 32h.

•

Master/slave ID0/1 are supported.

•

Headphone/line level outputs duplicating the main outputs, are supported, with gain control

from register 04h.

•

Wolfson 3D stereo enhanced sound supported.

•

Master volume control register maps to the location dependant on selected ID: (ID 00 or 01

uses master volume at register 02h, ID 10 uses 38h (surround volume) and ID11 uses 36h

(LFE, Centre volume).

GPIO PINS AND I

The AC’97 Revision 2.1 specification allows for provision of programmable IO pins, up to 16 in

number. Within the 48-pin TQFP package used, provision has been made for 3 pins to be used as

GPIO pins. These pins (numbers 43, 44, 48) are also used as I

channel operation.

When used as GPIO pins, the pins 43, 44, 48 are mapped respectively onto the bits 11,12,13 in the

AC-link slot 12. These optional locations may be configured in any way: as inputs or outputs,

supporting interrupt operation etc, offering maximum flexibility to the user. The appropriate GPIO

control registers are supported to control these pins.

When used as I2S pins, pin 43 becomes the shared LRCLK, with frequency fixed at 48kHz. Pins 44

and 48 become the output data, clocked out at the BITCLK rate. Thus to connect an external DAC,

configure it in I2S mode:

•

Connect BITCLK signal from the WM9704Q to the SCLK on the DAC.

•

Connect BITCLK from the AC’97 to BCLK on the DAC.

•

Connect pin 43 from the WM9704Q to the LRCLK on the DAC.

•

Connect one of the two data pins 44 or 48 on WM9704Q to the SDATA pin on the DAC.

Note that the DAC must support serial interface data rates at up to 12.5MHz (Wolfson DACs such as

the WM8725 and WM8733 support this).

I2S is enabled when GPIO is not enabled (GPIO Bit 0 = 0, PRA = 1 in register 3Eh) and vendor

specific I2S (bit 7) in register 5Ah is set.

The following table shows the connections to a typical I

WM9704Q CONNECTION

I

BITCLK

SCLK

BITCLK

BLCK

Pin 43 – GPIO1

LRCLK

SDATA on other external DAC

FORMAT pin - connect for I

Pin 44 – GPIO2 (surround data in ID00)

DEEMPH (if provided) - disable

Pin 48 – GPIO3 (LFE/centre data in ID00)

SDATA on external DAC

Table 2 Connection to External I

Configuration of these pins as GPIO is described in the control interface description.

3D STEREO ENHANCEMENT

This device contains a stereo enhancement circuit, designed to optimise the listening experience

when the device is used in a typical PC operating environment. That is, with a pair of speakers

placed either side of the monitor with little spatial separation. This circuit creates a difference signal

by differencing left and right channel playback data, then filters this difference signal using lowpass

and highpass filters whose time constants are set using external capacitors connected to the CX3D

pins 33 and 34. Typically the values of 100nF and 47nF set highpass and lowpass poles at about

100Hz and 1kHz respectively. This frequency band corresponds to the range over which the ear is

most sensitive to directional effects.