Production Data

WM9704Q

WOLFSON MICROELECTRONICS LTD

PD Rev 2.3 January 2001

21

SLOT 10: OPTIONAL MODEM LINE2 CODEC

Slot 10 is not supported.

SLOT 11: HANDSET DAC

Slot 11 is not supported.

SLOT 12: GPIO CONTROL

Data in this slot is applied to the GPIO pins, if they have been enabled via the control registers.

Note that only bits 11, 12 and 13 are supported, all others are ignored.

AC-LINK AUDIO INPUT FRAME (SDATA_IN)

SYNC

BIT_CLK

SDATA_IN

CODEC

READY

SLOT(1)

SLOT(2)

SLOT(12)

’0’

’0’

’0’

19

0

19

0

19

0

19

0

TAG PHASE

DATA PHASE

20.8

µS (48kHz)

12.288MHz

81.4nS

END OF PREVIOUS

AUDIO FRAME

TIME SLOT ’VALID’ BITS

(’1’ = TIME SLOT CONTAINS

VALID PCM DATA)

SLOT (1)

SLOT (2)

SLOT (3)

SLOT (12)

Figure 11 AC-link Audio Input Frame

The audio input frame data streams correspond to the multiplexed bundles of all digital input data

targeting the AC’97 controller. As is the case for audio output frame, each AC-link audio input frame

consists of 12, 20-bit time slots.

Slot 0 is a special reserved time slot containing 16-bits, which are used for AC-link protocol

infrastructure.

Within slot 0 the first bit is a global bit (SDATA_IN slot 0, bit 15) which flags whether the WM9704Q

is in the Codec Ready state or not. If the Codec Ready bit is a 0, this indicates that the WM9704Q is

not ready for normal operation. This condition is normal following the desertion of power on reset for

example, while the WM9704Q’s voltage references settle. When the AC-link Codec Ready indicator

bit is a 1, it indicates that the AC-link and the WM9704Q control and status registers are in a fully

operational state. The AC’97 controller must further probe the Powerdown Control/Status Register to

determine exactly which subsections, if any, are ready.

Prior to any attempts at putting the WM9704Q into operation the AC’97 controller should poll the first

bit in the audio input frame (SDATA_IN slot 0, bit 15) for an indication that the WM9704Q has gone

Codec Ready.

Once the WM9704Q is sampled Codec Ready then the next 12 bit positions sampled by the AC’97

controller indicate which of the corresponding 12 time slots are assigned to input data streams, and

that they contain valid data. Figure 11 illustrates the time slot based AC-link protocol.

There are several subsections within the WM9704Q that can independently go busy/ready. It is the

responsibility of the WM9704Q controller to probe more deeply into the WM9704Q register file to

determine which the WM9704Q subsections are actually ready.