WM9704Q

Production Data

WOLFSON MICROELECTRONICS LTD

PD Rev 2.3 January 2001

28

Figure 13 illustrates one example of a procedure to do a complete powerdown of the WM9704Q.

From normal operation sequential writes to the Powerdown Register are performed to powerdown the

WM9704Q a piece at a time. After everything has been shut off (PR0 to PR3 set), a final write (of

PR4) can be executed to shut down the WM9704Q’s digital interface (AC-link).

The part will remain in sleep mode with all its registers holding their static values. To wake up the

WM9704Q, the AC’97 controller will send a pulse on the sync line issuing a warm reset. This will

restart the WM9704Q’s digital interface (resetting PR4 to 0). The WM9704Q can also be woken up

with a cold reset. A cold reset will cause a loss of values of the registers, as a cold reset will set them

to their default states. When a section is powered back on, the Powerdown Control/Status Register

(26h) should be read to verify that the section is ready (i.e. stable) before attempting any operation

that requires it.

Alternatively if RESETB is held low, all PR bits are held set so the device is held powered off until

RESETB is taken high again.

PR1 = 1

PR2 = 1

PR4 = 1

ADCs OFF

PR0

DACs OFF

PR1

ANALOGUE

OFF PR2

OR PR3

DIGITAL I/F

OFF PR4

WARM RESET

PR1 = 0 AND

DAC = 1

PR2 = 0 AND

ANL = 1

SHUT OFF

CODA LINK

Figure 14 The WM9704Q Powerdown/Flow with Analogue Still Alive

Figure 14 illustrates a state when all the mixers should work with the static volume settings that are

contained in their associated registers. This is used when the user is playing a CD (or external

LINE_IN source) through WM9704Q to the speakers but has most of the system in low power mode.

The procedure for this follows the previous procedure except that the analogue mixer is never shut

down.

POWERDOWN CONTROL/STATUS REGISTER (INDEX 26h)

Note that in order to go into ultimate low power mode, PR5 is required to be set which turns off the

oscillator circuit. Asserting SYNC resets the PR5 bit and re-starts the oscillator in the same was as

the AC link is restarted.

Also when RESETB pin is asserted low, all PR bits are over-ridden and the entire device is powered

off to ultra low power state for as long as RESETB = low. On releasing RESETB, the device is reset

(all active) and powered up.