WM9704Q

Production Data

WOLFSON MICROELECTRONICS LTD

PD Rev 2.3 January 2001

30

REGISTERS 36h AND 38h – 6 CHANNEL VOLUME CONTROL

These read/write registers control the output volume of the optional four PCM channels. Note that as

WM9704Q only supports 4 internal DACs, depending upon which ID has been selected via the CID

pins 45 and 46, these registers may or may not have effect. The fields behave the same as the

master volume control register, which offers attenuation but no gain. If gain is required then the PCM

DAC mixer PGAs appropriate to each DAC should be used.

If Quad Mode is selected and ID = 10 or 11, then either 36h or 38h will control the level of the rear

DAC outputs onto the line level pins 39 and 41. Surround data which is mapped from the surround

data slots out onto the GPIO pins as I

however, mute the data to all 0s.

GPIO FUNCTION

Note that only the three GPIO pins are supported, GPIO 11 to 13. These pins are available to the

user, unless used for I

REGISTER 4Ch – GPIO PIN CONFIGURATION REGISTER

The GPIO Pin Configuration is a read/write register that specifies whether a GPIO pin is configured

for input (1) or for output (0), and is accessed via the standard slot 1 and 2 command address/data

protocols.

If a GPIO pin is implemented, the respective GCx bit should be read/writeable and set to 1. If a GPIO

is not implemented, then the respective GCx bit is read-only and set to 0. This informs the software

how many GPIO pins have been implemented. It is up to the AC’97 Digital Controller to send the

desired GPIO pin value over output slot 12 in the outgoing stream of the AC-link before configuring

any of these bits for output. The default value after cold or register reset for this register (3800h) is all

pins configured as inputs.

REGISTER 4Eh – GPIO PINS POLARITY/TYPE

The GPIO Pin Polarity/Type is a read/write register that defines GPIO input polarity (0 = Low,

1 = High active) when a GPIO pin is configured as an Input. It defines GPIO output type

(1 = CMOS, 0 = OPEN-DRAIN) when a GPIO pin is configured as an output.

The default value after cold or register reset for this register (FFFFh) is all pins active high.

Non-implemented GPIO pins always return 1s.

REGISTER 50h – GPIO PIN STICKY CONTROL

The GPIO Pin Sticky is a read/write register that defines GPIO Input Type (0 = Non-sticky,

1 = Sticky) when a GPIO pin is configured as an input. GPIO inputs configured as sticky are cleared

by writing a 0 to the corresponding bit of the GPIO pin status register 54h (see below), and by reset.

The default value after cold or register reset for this register (0000h) is all pins Non-sticky.

Unimplemented GPIO pins always return 0s. Sticky is defined as edge-sensitive, Non-sticky as level

sensitive.

REGISTER 52h – GPIO PIN WAKE-UP CONTROL

The GPIO Pin Wake-up is a read/write register that provides a mask for determining if an input GPIO

change will generate a wake-up or GPIO_INT (0 = No, 1 = Yes). When the AC-Link is powered down

(Register 26h PR4 = 1 for primary codecs), a wake-up event will trigger the assertion of SDATA_IN.

When AC-link is powered up, a wake-up event will appear as GPIO_INT = 1 on bit 0 of input slot 12.

GPIO_INT is also flagged when the link is active.

An AC-link wake-up interrupt is defined as a 0 to 1 transition on SDATA_IN when the AC-Link is

powered down (Register 26h PR4 = 1). GPIO bits that have been programmed as inputs, sticky and

pin wake-up, upon transition either (high-to-low) or (low-to-high) depending on pin polarity, will cause

an AC-link wake-up event (transition of SDATA_IN from 0 to 1), if and only if the AC-link was

powered down.

The default value after cold or register reset for this register (0000h) defaults to all 0s specifying no

wake-up event. Non-implemented GPIO pins always return 0s.