HT82K75R datasheet(31/66 Pages) HOLTEK

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HT82M75R/HT82M75RE

HT82K75R/HT82K75RE

Rev. 1.10

June 11, 2010

SPI Serial Interface

The device includes one SPI Serial Interfaces. The SPI

interface is a full duplex serial data link, originally de-

signed by Motorola, which allows multiple devices con-

nected to the same SPI bus to communicate with each

other. The devices communicate using a master/slave

technique where only the single master device can initi-

ate a data transfer. A simple four line signal bus is used

for all communication.

SPI Interface Communication

Four lines are used for each function. These are, SDI -

Serial Data Input, SDO - Serial Data Output, SCK - Se-

rial Clock and SCS - Slave Select. Note that the condi-

tion of the Slave Select line is conditioned by the CSEN

bit in the SBCR control register. If the CSEN bit is high

then the SCS line is active while if the bit is low then the

SCS line will be I/O mode. The accompanying timing di-

agram depicts the basic timing protocol of the SPI bus.

SPI Registers

There are three registers for control of the SPI Interface.

These are the SBCR register which is the control regis-

ter and the SBDR which is the data register and SPIR

SBCR register is used to setup the required setup pa-

rameters for the SPI bus and also used to store associ-

ated operating flags, while the SBDR register is used for

data storage.

The SPIR register is used to select SPI mode, clock po-

larity edge selection and SPI enable or disable selec-

tion.

After Power on, the contents of the SBDR register will

be in an unknown condition while the SBCR register will

default to the condition below:

CKS

SBEN

MLS

CSEN WCOL

TRF

00000

Note that data written to the SBDR register will only be

written to the TXRX buffer, whereas data read from the

SBDR register will actual be read from the register.

SPI Bus Enable/Disable

To enable the bus, the SBEN bit should be set high,

then wait for data to be written to the SBDR (TXRX

buffer) register. For the Master Mode, after data has

been written to the SBDR (TXRX buffer) register then

transmission or reception will start automatically. When

all the data has been transferred, the TRF bit should be

set. For the Slave Mode, when clock pulses are re-

ceived on SCK, data in the TXRX buffer will be shifted

out or data on SDI will be shifted in.

To Disable the SPI bus SCK, SDI, SDO, SCS should be

I/O mode.

Bit No.

Label

R/W

Function

SPI_CPOL

R/W

0: clock polarity falling (default falling)

1: clock polarity rising

SPI_MODE

R/W

0: SPI output the data in the rising edge(polarity=1) or falling edge (polarity=0);

SPI read data in the in the falling edge(polarity=1) or rising edge (polarity=0);

(default)

1: SPI first output the data immediately after the SPI is enable. And SPI output

the data in the falling edge(polarity=1) or rising edge (polarity=0); SPI read data

in the in the rising edge(polarity=1) or falling edge (polarity=0)

SPI_CSEN

R/W

0: SPI_CSEN disable, SCS define as GPIO (default disable)

1: SPI_CSEN Enable , this bit is used to enable/disable software CSEN function

SPI_EN

R/W

This bit control the shared PIN (SCS, SDI, SDO and SCK) is SPI or GPIO mode

0: I/O mode (default)

1: SPI mode

7~4

Reserved bit

R/W

Always 0

SPIR Register

HT82K75R 数据表(PDF) 31 Page - Holtek Semiconductor Inc

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