HT82K75R datasheet(33/66 Pages) HOLTEK

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HT82M75R/HT82M75RE

HT82K75R/HT82K75RE

Rev. 1.10

June 11, 2010

SPI Operation

All communication is carried out using the 4-line inter-

face for both Master or Slave Mode. The timing diagram

shows the basic operation of the bus.

The CSEN bit in the SBCR register controls the SCS

line of the SPI interface. Setting this bit high, will enable

the SPI interface by allowing the SCS line to be active,

which can then be used to control the SPI inteface. If the

CSEN bit is low, the SCS line will be in a floating condi-

tion and can therefore not be used for control of the SPI

interface. The SBEN bit in the SBCR register must also

be high which will place the SDI line in a floating condi-

tion and the SDO line high. If in the Master Mode the

SCK line will be either high or low depending upon the

clock polarity control bit in SPIR register. If in the Slave

Mode the SCK line will be in a floating condition. If SBEN

is low then the bus will be disabled and SCS, SDI, SDO

and SCK will all be I/O mode.

In the Master Mode, the Master will always generate the

clock signal. The clock and data transmission will be ini-

tiated after data has been written to the SBDR register.

In the Slave Mode, the clock signal will be received from

an external master device for both data transmission or

reception. The following sequences show the order to

be followed for data transfer in both Master and Slave

Mode:

· Master Mode

Step 1. Select the clock source using the CKS bit in

the SBCR control register

Step 2. Setup the M0 and M1 bits in the SBCR control

required Baud rate. Values of 00, 01 or 10 can

be selected.

Step 3. Setup the CSEN bit and setup the

MLS bit to choose if the data is MSB or LSB

first, this must be same as the Slave device.

Step 4. Setup the SBEN bit in the SBCR

control register to enable the SPI interface.

Step 5. For write operations: write the data to the

SBDR register, which will actually

place the data into the TXRX buffer. Then use

the SCK and SCS lines to output the data.

Goto to step 6.For read operations: the data

transferred in on the SDI line will be

stored in the TXRX buffer until all the data has

been received at which point it will be latched

into the SBDR register.

Step 6. Check the WCOL bit, if set high then a

collision error has occurred so return to step5.

If equal to zero then go to the following step.

Step 7. Check the TRF bit or wait for an SPI serial

bus interrupt.

Step 8. Read data from the SBDR register.

Step 9. Clear TRF.

Step10. Goto step 5.

· Slave Mode:

Step 1. The CKS bit has a don

¢t care value in the

slave mode.

Step 2. Setup the M0 and M1 bits to 11 to select the

Slave Mode. The CKS bit is don

¢t care.

Step 3. Setup the CSEN bit and setup the

MLS bit to choose if the data is MSB or LSB

first, this must be same as the Master device.

Step 4. Setup the SBEN bit in the SBCR

control register to enable the SPI interface.

Step 5. For write operations: write data to the

SBDR register, which will actually

place the data into the TXRX register, then

wait for the master clock and SCS signal.

After this goto Step 6.

For read operations: the data transferred in

on the SDI line will be stored in the

TXRX buffer until all the data has been

received at which point it will be latched into

the SBDR register.

Step 6. Check the WCOL bit, if set high then a

collision error has occurred so return to step5.

If equal to zero then goto the following step.

Step 7. Check the TRF bit or wait for an SPI serial bus

interrupt.

Step 8. Read data from the SBDR register.

Step 9. Clear TRF

Step10. step 5

HT82K75R 数据表(PDF) 33 Page - Holtek Semiconductor Inc

HT82K75R 数据表(HTML) 33 Page - Holtek Semiconductor Inc

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