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HT82K75R 数据表(PDF) 34 Page - Holtek Semiconductor Inc |
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HT82K75R 数据表(HTML) 34 Page - Holtek Semiconductor Inc |
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34 / 66 page ![]() HT82M75R/HT82M75RE HT82K75R/HT82K75RE Rev. 1.10 34 June 11, 2010 SPI Configuration Options and Status Control One option is to enable the operation of the WCOL, write collision bit, in the SBCR register. Some control in SPIR register. The SPI_CPOL select the clock polarity of the SCK line . The SPI_MODE select SPI data output mode. SPI include four pins , can share I/O mode status . The status control combine with four bits for SPIR and SBCR regis- ter. Include SPI_CSEN , SPI_EN for SPIR register and CSEN ,SBEN for SBCR register. SPIR(22H) SBCR(23H) I/O Status Note SPI_EN SPI_CSEN SBEN CSEN SPI SCS 0 x x x I/O mode I/O mode 1 x 0 x I/O mode I/O mode 1 0 1 x SPI mode I/O mode SCS not Floating 1 1 1 0 SPI mode I/O mode SCS not Floating 1 1 1 1 SPI mode SCS mode The SPI enable, SCS, SDI, SDO, SCK the internal Pull-high function is invalid. Note: X: don ¢t care Error Detection The WCOL bit in the SBCR register is provided to indi- cate errors during data transfer. The bit is set by the Se- rial Interface but must be cleared by the application program. This bit indicates a data collision has occurred which happens if a write to the SBDR register takes place during a data transfer operation and will prevent the write operation from continuing. The bit will be set high by the Serial Interface but has to be cleared by the user application program. The overall function of the WCOL bit can be disabled or enabled by a configuration option. Programming Considerations When the device is placed into the Power Down Mode note that data reception and transmission will continue. The TRF bit is used to generate an interrupt when the data has been transferred or received. S B C R R e g i s t e r b 7 b 0 C K S M 1 M 0 S B E N M L S C S E N W C O L T R F T r a n s m i t t / R e c e i v e f l a g 0 : N o t c o m p l e t e 1 : T r a n s m i s s i o n / r e c e p t i o n c o m p l e t e W r i t e c o l l i s i o n b i t 0 : C o l l i s i o n f r e e 1 : C o l l i s i o n d e t e c t e d S e l e c t i o n s i g n a l e n a b l e / d i s a b l e b i t 0 : S C S f l o a t i n g f o r I / O m o d e 1 : E n a b l e M S B / L S B f i r s t b i t 0 : L S B s h i f t f i r s t 1 : M S B s h i f t f i r s t S e r i a l B u s e n a b l e / d i s a b l e b i t 0 : D i s a b l e 1 : E n a b l e M a s t e r / S l a v e / B a u d r a t e b i t s M a s t e r , b a u d r a t e : f S P I M a s t e r , b a u d r a t e : f S P I / 4 M a s t e r , b a u d r a t e : f S P I / 1 6 S l a v e m o d e M 1 0 0 1 1 M 0 0 1 0 1 C l o c k s o u r c e s e l e c t b i t 0 : f S P I = f S Y S / 2 1 : f S P I = f S Y S SPI Interface Control Register |
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