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Freescale Semiconductor

MC44CC373

MODES OF OPERATION AND FUNCTIONAL DESCRIPTION

POWER ON SETTINGS

At power-on, the modulators are configured with pre-programmed default settings as listed in Table 2.

POWER ON RESET

A power-on reset circuit holds the digital portion in reset

until the power supply has stabilized. Additionally a delay of

approximately 2 seconds allows the crystal oscillator to stabi-

lize before the digital section begins normal operation.

TRANSIENT OUTPUT INHIBIT

To minimize the risk of interference to other channels while

the UHF PLL is acquiring a lock on the desired frequency, the

Sound and Video modulators are turned OFF during a time

out period in two cases: Power On and UHF oscillator power

On (OSC bit switched from OFF to normal operation). There

is a time out of 262 ms until the output is enabled. This lets

the UHF PLL settle to its programmed frequency.

STANDBY MODES

During standby mode, the modulator is switched to low

power consumption. The sound oscillator, UHF oscillator, and

the video and sound modulator section’s bias are internally

The standby mode is set with a combination of 3 bits:

OSC=1, SO=1 and ATT=1 for MC44CC373/374CAxxx

OSC=0, SO=1 and ATT=1 for MC44CC374T1Axx

Programming of the Frequency Registers or the Optional

Control Registers is not allowed in Standby Mode.

SYSTEM L OR B/G SELECTION

The SYSL enable control bit internally switches the follow-

ing functions:

•

SYSL = 0 enables B/G system

— Video modulation polarity: Negative

— Sound modulation: FM

•

SYSL = 1 enables L system

— Video modulation polarity: Positive

— Sound modulation AM

CRYSTAL REFERENCE OSCILLATOR

The reference crystal frequency is 4.0 MHz, the same as

for the legacy modulators.

The reference crystal oscillator if followed by a fixed di-

vide-by-128, resulting in a reference frequency of 31.25 kHz

for the phase detector.

UHF PLL SECTION

The UHF VCO runs at twice the desired RF frequency and

is divided by 2 before it is sent to the divide-by-8 prescaler

and then the programmable divider.

The programmable divider division-ratio is controlled by

the state of control bits N0 to N11 and is the binary number

quency. The divider-ratio N for a desired frequency F (in

MHz) is given by:

with:

NOTE:

Programming a division-ratio N = 0 is not allowed.

Programming of the N value must be performed while

the modulator is in normal mode, not standby mode.

Table 2. Power On Default Settings

Operating Mode

Default Values

Part Number

MC44CC373CA

MC44CC373CAS

MC44CC374CA

MC44CC374T1A

UHF oscillator frequency (MHz)

591.25

591.25

591.25

871.25

1. Refer to application note to obtain 82 dB

μV or other RF levels.

89

89

89

89

Sound frequency (MHz)

5.5

5.5

5.5

5.5

Sound reference frequency (kHz)

31.25

31.25

31.25

31.25

Logic Output Port (logic level)

Low

Low

Low

Low

Picture to sound ratio (dB)

12

12

12

12

Peak White Clip (state)

On

On

On

On

System Standards

B/G

B/G

B/G

B/G

N

2F

×

()

16

------------------ 128

4

----------

×

=

N

2048 N11 1024 N10

…… 4N2 2 N1 N0

+

×

+

×

++

×

+

×

=