MC44CC373CAS datasheet(9/28 Pages) FREESCALE

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MC44CC373

HIGH SPEED I2C CONTROL INTERFACE OPERATION

The modulator chip’s digital control interface is compatible

with the I2C bus standard. The two pins used for the I2C bus

are the clock (SCL) and data (SDA). The data pin is bidirec-

tional.

The I2C interface lines are 5 Volt tolerant. Therefore, they

can be pulled up to 5 Volts, if required, to interface with the

microprocessor in a given application.

NOTE:

If the MC44CC373/4 modulator is powered down, it

will load the I2C bus by means of leakage current

passing through the stacked ESD protection diodes

on the SCL and SDA pins.

The input control data stream is clocked in on the rising

edge of SCL, with the most significant bit, MSB, first. The sev-

en-bit IC Address and R/W bit are in the first byte sent. This

allows the IC to determine if it is the device that is being com-

municated with. After that, an even number of control data

bytes, 8-bits each, sent to configure the IC. The data stored

in the input control register is loaded into the appropriate de-

vice registers during the acknowledge, ACK, bit time.

The Master controls the clock line, whether writing to the

part or reading from it. After each byte that is sent, the device

that receives it, sends an acknowledge bit back to the master.

After the last data byte and ACK, the master sends a Stop

Condition to terminate the write cycle.

Status data can be read back from the modulator chip. The

output status data is clocked out on the falling edge of SCL

and is valid on the rising edge, with the MSB first.

IC Device Address

Since the I2C bus is a two-wire bus that does not have a

separate chip-select line, each IC on the bus has a unique

address. This address must be sent each time an IC is com-

municated with. The address is the first seven bits that are

sent to the IC as shown in Table 9. The eighth bit sent is the

R/W bit, it determines whether the master will read from or

write to the IC.

Address bit A1 selects one of two possible addresses. The

chip address is defined by the orderable part number as listed

in Table 10. The RW bit determines if the master is requesting

a read or write. RW = 0 = write and RW = 1 = read.

I2C Write Mode Format

In the write mode, each ninth data bit is an acknowledge

bit (ACK) as shown in Figure 5. During this time, the Master

lets go of the bus, the external pull-up resistor pulls the signal

high and sends a logic 1 and the Modulator circuit (slave) an-

swers on the data line by pulling it low.

Besides the first byte with the chip address, the circuit

needs two or more data bytes for operation.

The programming of the MC44CC37xxxxx devices is sim-

ilar to the legacy devices. That is, they may be programmed

with either two or four data bytes, after the chip address.

Table 11 shows the permitted data bytes, and the order in

which they can be sent, to program the MC44CC373/374 de-

vices. Examples 1 and 2 are the same as the legacy modula-

tors.

The control data bytes all contain an address function bit

(the MSB) which lets the IC distinguish between the frequen-

cy information and control information. If the address function

bit is a logic 1, the following bytes contain control information.

The frequency information has the address function bit that is

set to a logic 0. This allows the frequency or the control infor-

mation to be sent first as shown inn Examples 3,and 4.

The MC44BS373/4 legacy family of RF modulators re-

quired only two words of data (four bytes) for full configura-

tion. The new CMOS devices have two additional (optional)

control words that can be used to access some new features.

These features include changing the output power, using a

different frequency crystal, and adjusting the peak white clip

levels. These new Option Control words do not need to be

sent unless access to these new features is desired. The de-

fault values for these functions will allow the device to work

the same way as the MC44BS373/4 devices did.

Example 5 shows how the new Option Control words are

to be sent. OC1 follows the Control word and OC2 follows

OC1.

Example 6 shows the Frequency word being sent first fol-

lowed by the Control bytes.

Table 9. IC Address Byte Format

IC Address

Read/

Write

R/W

Table 10. Chip Address by Orderable Part Number

Orderable Part Number

IC Address Byte

Mode

Binary

Hex

MC44CC373CA, MC44CC374CA,

MC44CC374T1A

Write

1100_1010

0xCA

Read

1100_1011

0xCB

MC44CC373CAS

Write

1100_1110

0xCE

Read

1100_1111

0xCF

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