PSD813F2V datasheet(54/109 Pages) STMICROELECTRONICS

54 / 109 page

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Product(s)

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Product(s)

PSD813F2V, PSD854F2V

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Doc ID 10552 Rev 3

Table 20. Port Operating Mode Settings

Note: 1. N/A = Not Applicable

2. The direction of the Port A,B,C, and D pins are controlled by the Direction Register ORed with the individual output enable product

term (.oe) from the CPLD AND Array.

3. Any of these three methods enables the JTAG pins on Port C.

Table 21. I/O Port Latched Address Output Assignments

Note: 1. N/A = Not Applicable.

Mode

Defined in

PSDabel

Defined in PSD

Configuration

Control

Setting

Direction

Setting

JTAG Enable

MCU I/O

Declare pins only

N/A1

1 = output,

0 = input

(Note 2)

N/A

PLD I/O

Logic equations

N/A

(Note 2)

N/A

Data Port (Port A)

N/A

Specify bus type

N/A

Address Out

(Port A,B)

Declare pins only

N/A

1 (Note 2)

N/A

Address In

(Port A,B,C,D)

Logic for equation

Input Macrocells

N/A

Peripheral I/O

(Port A)

Logic equations

(PSEL0 & 1)

N/A

PIO bit = 1

N/A

JTAG ISP (Note 3)

JTAGSEL

JTAG

Configuration

N/A

JTAG_Enable

MCU

Port A (PA3-PA0)

Port A (PA7-PA4)

Port B (PB3-PB0)

Port B (PB7-PB4)

8051XA (8-Bit)

N/A1

Address a7-a4

Address a11-a8

N/A

80C251

(Page Mode)

N/A

Address a11-a8

Address a15-a12

All Other

8-Bit Multiplexed

Address a3-a0

Address a7-a4

Address a3-a0

Address a7-a4

8-Bit

Non-Multiplexed Bus

N/A

Address a3-a0

Address a7-a4

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