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PSD813F2V 数据表(PDF) 97 Page - STMicroelectronics |
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PSD813F2V 数据表(HTML) 97 Page - STMicroelectronics |
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97 / 109 page  Obsolete Product(s) - Obsolete Product(s) 97/109 PSD813F2V, PSD854F2V Doc ID 10552 Rev 3 Figure 50. ISC Timing Table 67. ISC Timing (5V devices) Note: 1. For non-PLD Programming, Erase or in ISC by-pass mode. 2. For Program or Erase PLD only. Symbol Parameter Conditions -70 -90 -15 Unit MinMax MinMax MinMax tISCCF Clock (TCK, PC1) Frequency (except for PLD) (Note 1) 20 18 14 MHz tISCCH Clock (TCK, PC1) High Time (except for PLD) (Note 1) 23 26 31 ns tISCCL Clock (TCK, PC1) Low Time (except for PLD) (Note 1) 23 26 31 ns tISCCFP Clock (TCK, PC1) Frequency (PLD only) (Note 2) 222 MHz tISCCHP Clock (TCK, PC1) High Time (PLD only) (Note 2) 240 240 240 ns tISCCLP Clock (TCK, PC1) Low Time (PLD only) (Note 2) 240 240 240 ns tISCPSU ISC Port Set Up Time 7 8 10 ns tISCPH ISC Port Hold Up Time 5 5 5 ns tISCPCO ISC Port Clock to Output 21 23 25 ns tISCPZV ISC Port High-Impedance to Valid Output 21 23 25 ns tISCPVZ ISC Port Valid Output to High-Impedance 21 23 25 ns ISCCH TCK TDI/TMS ISC OUTPUTS/TDO ISC OUTPUTS/TDO t ISCCL t ISCPH t ISCPSU t ISCPVZ t ISCPZV t ISCPCO t AI02865 |
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