PSD813F2V datasheet(26/109 Pages) STMICROELECTRONICS

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Doc ID 10552 Rev 3

Data Toggle

Checking the Toggle Flag Bit (DQ6) is a method of

determining whether a Program or Erase cycle is

in progress or has completed. Figure 8 shows the

Data Toggle algorithm.

When the MCU issues a Program instruction, the

embedded algorithm within the PSD begins. The

MCU then reads the location of the byte to be pro-

grammed in Flash memory to check status. The

Toggle Flag Bit (DQ6) of this location toggles each

time the MCU reads this location until the embed-

ded algorithm is complete. The MCU continues to

read this location, checking the Toggle Flag Bit

(DQ6) and monitoring the Error Flag Bit (DQ5).

When the Toggle Flag Bit (DQ6) stops toggling

(two consecutive reads yield the same value), and

the Error Flag Bit (DQ5) remains ’0,’ the embed-

ded algorithm is complete. If the Error Flag Bit

(DQ5) is '1,' the MCU should test the Toggle Flag

Bit (DQ6) again, since the Toggle Flag Bit (DQ6)

may have changed simultaneously with the Error

Flag Bit (DQ5, see Figure 8).

The Error Flag Bit (DQ5) is set if either an internal

time-out occurred while the embedded algorithm

attempted to program the byte, or if the MCU at-

tempted to program a '1' to a bit that was not

erased (not erased is logic '0').

It is suggested (as with all Flash memories) to read

the location again after the embedded program-

ming algorithm has completed, to compare the

byte that was written to Flash memory with the

byte that was intended to be written.

When using the Data Toggle method after an

Erase cycle, Figure 8 still applies. the Toggle Flag

Bit (DQ6) toggles until the Erase cycle is complete.

A '1' on the Error Flag Bit (DQ5) indicates a time-

out condition on the Erase cycle; a '0' indicates no

error. The MCU can read any location within the

sector being erased to get the Toggle Flag Bit

(DQ6) and the Error Flag Bit (DQ5).

PSDsoft Express generates ANSI C code func-

tions which implement these Data Toggling algo-

rithms.

Unlock Bypass (PSD833F2x, PSD834F2x,

PSD853F2x, PSD854F2x)

The Unlock Bypass instructions allow the system

to program bytes to the Flash memories faster

than using the standard Program instruction. The

Unlock Bypass mode is entered by first initiating

two Unlock cycles. This is followed by a third

WRITE cycle containing the Unlock Bypass code,

20h (as shown in Table 9., page 21).

The Flash memory then enters the Unlock Bypass

mode. A two-cycle Unlock Bypass Program in-

struction is all that is required to program in this

mode. The first cycle in this instruction contains

the Unlock Bypass Program code, A0h. The sec-

ond cycle contains the program address and data.

Additional data is programmed in the same man-

ner. These instructions dispense with the initial

two Unlock cycles required in the standard Pro-

gram instruction, resulting in faster total Flash

memory programming.

During the Unlock Bypass mode, only the Unlock

Bypass Program and Unlock Bypass Reset Flash

instructions are valid.

To exit the Unlock Bypass mode, the system must

issue the two-cycle Unlock Bypass Reset Flash in-

struction. The first cycle must contain the data

90h; the second cycle the data 00h. Addresses are

Don’t Care for both cycles. The Flash memory

then returns to READ Mode.

Figure 8. Data Toggle Flowchart

READ

DQ5 & DQ6

START

READ DQ6

FAIL

PASS

AI01370B

DQ6

TOGGLE

YES

DQ5

= 1

YES

DQ6

TOGGLE

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