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PSD813F2V 数据表(PDF) 61 Page - STMicroelectronics |
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PSD813F2V 数据表(HTML) 61 Page - STMicroelectronics |
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61 / 109 page  Obsolete Product(s) - Obsolete Product(s) 61/109 PSD813F2V, PSD854F2V Doc ID 10552 Rev 3 External Chip Select The CPLD also provides three External Chip Se- lect (ECS0-ECS2) outputs on Port D pins that can be used to select external devices. Each External Chip Select (ECS0-ECS2) consists of one product term that can be configured active High or Low. The output enable of the pin is controlled by either the output enable product term or the Direction Register. (See Figure 31.) Figure 31. Port D External Chip Select Signals POLARITY BIT PD2 PIN PT2 ECS2 DIRECTION REGISTER POLARITY BIT PD1 PIN PT1 ECS1 ENABLE (.OE) ENABLE (.OE) DIRECTION REGISTER POLARITY BIT PD0 PIN PT0 ECS0 ENABLE (.OE) DIRECTION REGISTER AI02890 |
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