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PSD813F2V 数据表(PDF) 91 Page - STMicroelectronics

部件名 PSD813F2V
功能描述  Flash in-system programmable (ISP) peripherals for 8-bit MCUs, 3.3 V
PDF  109 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

PSD813F2V 数据表(HTML) 91 Page - STMicroelectronics

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PSD813F2V, PSD854F2V
Doc ID 10552 Rev 3
Table 57. WRITE Timing (5V devices)
Note: 1. Any input used to select an internal PSD function.
2. In multiplexed mode, latched address generated from ADIO delay to address output on any port.
3. WR has the same timing as E, LDS, UDS, WRL, and WRH signals.
4. Assuming data is stable before active WRITE signal.
5. Assuming WRITE is active before data becomes valid.
6. TWHAX2 is the address hold time for DPLD inputs that are used to generate Sector Select signals for internal PSD memory.
Symbol
Parameter
Conditions
-70
-90
-15
Unit
MinMax
MinMax
MinMax
tLVLX
ALE or AS Pulse Width
15
20
28
ns
tAVLX
Address Setup Time
(Note 1)
4
6
10
ns
tLXAX
Address Hold Time
(Note 1)
7
8
11
ns
tAVWL
Address Valid to Leading
Edge of WR
(Notes 1,3)
815
20
ns
tSLWL
CS Valid to Leading Edge of WR
(Note 3)
12
15
20
ns
tDVWH
WR Data Setup Time
(Note 3)
25
35
45
ns
tWHDX
WR Data Hold Time
(Note 3)
455
ns
tWLWH
WR Pulse Width
(Note 3)
31
35
45
ns
tWHAX1
Trailing Edge of WR to Address Invalid
(Note 3)
6
8
10
ns
tWHAX2
Trailing Edge of WR to DPLD Address
Invalid
(Note 3,6)
000
ns
tWHPV
Trailing Edge of WR to Port Output
Valid Using I/O Port Data Register
(Note 3)
27
30
38
ns
tDVMV
Data Valid to Port Output Valid
Using Macrocell Register
Preset/Clear
(Notes 3,5)
42
55
65
ns
tAVPV
Address Input Valid to Address
Output Delay
(Note 2)
20
25
30
ns
tWLMV
WR Valid to Port Output Valid Using
Macrocell Register Preset/Clear
(Notes 3,4)
48
55
65
ns



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