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ST10F276Z5 数据表(PDF) 112 Page - STMicroelectronics |
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ST10F276Z5 数据表(HTML) 112 Page - STMicroelectronics |
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112 / 239 page  System reset ST10F276Z5 112/239 Figure 27. Asynchronous hardware RESET (EA = 0) 1. This timing can be longer than Port0 settling time + PLL synchronization (if needed, that is P0(15:13) changed). It can longer than 500ns to take into account of Input Filter on RSTIN pin. 2. 2. 3 to 8 TCL depending on clock source selection Exit from asynchronous reset state When the RSTIN pin is pulled high, the device restarts: as already mentioned, if internal FLASH is used, the restarting occurs after the embedded FLASH initialization routine is completed. The system configuration is latched from Port0: ALE, RD and WR/WRL pins are driven to their inactive level. The device starts program execution from memory location 00'0000h in code segment 0. This starting location will typically point to the general initialization routine. Timing of asynchronous Hardware Reset sequence are summarized in Figure 26 and Figure 27. RSTF P0[15:13] P0[12:2] transparent not t. transparent not t. P0[1:0] not t. not transparent 3..8 TCL2) RST Latching point of Port0 for system start-up configuration RPD ALE 1) not transparent not transparent (After Filter) RSTIN ≤ 500 ns ≥ 50 ns ≤ 500 ns ≥ 50 ns 8 TCL 3..4 TCL |
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