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ST10F276Z5

System reset

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19.3

Synchronous reset (warm reset)

A synchronous reset is triggered when RSTIN pin is pulled low while RPD pin is at high

level. In order to properly activate the internal reset logic of the device, the RSTIN pin must

be held low, at least, during 4 TCL (2 periods of CPU clock): refer also to Section 19.1 for

details on minimum reset pulse duration. The I/O pins are set to high impedance and

RSTOUT pin is driven low. After RSTIN level is detected, a short duration of a maximum of

12 TCL (six periods of CPU clock) elapses, during which pending internal hold states are

cancelled and the current internal access cycle if any is completed. External bus cycle is

aborted. The internal pull-down of RSTIN pin is activated if bit BDRSTEN of SYSCON

after a reset sequence.

Short and long synchronous reset

Once the first maximum 16 TCL are elapsed (4+12TCL), the internal reset sequence starts.

It is 1024 TCL cycles long: at the end of it, and after other 8TCL the level of RSTIN is

sampled (after the filter, see RSTF in the drawings): if it is already at high level, only Short

Reset is flagged (Refer to Chapter 19: System reset for details on reset flags); if it is

recognized still low, the Long reset is flagged as well. The major difference between Long

and Short reset is that during the Long reset, also P0(15:13) become transparent, so it is

possible to change the clock options.

Warning:

In case of a short pulse on RSTIN pin, and when Bidirectional

reset is enabled, the RSTIN pin is held low by the internal

circuitry. At the end of the 1024 TCL cycles, the RTSIN pin is

released, but due to the presence of the input analog filter the

internal input reset signal (RSTF in the drawings) is released

later (from 50 to 500 ns). This delay is in parallel with the

additional 8 TCL, at the end of which the internal input reset

line (RSTF) is sampled, to decide if the reset event is Short or

Long. In particular:

●

If 8 TCL > 500 ns (FCPU < 8 MHz), the reset event is always recognized as Short

●

If 8 TCL < 500 ns (FCPU > 8 MHz), the reset event could be recognized either as Short

or Long, depending on the real filter delay (between 50 and 500 ns) and the CPU

frequency (RSTF sampled High means Short reset, RSTF sampled Low means Long

reset). Note that in case a Long Reset is recognized, once the 8 TCL are elapsed, the

P0(15:13) pins becomes transparent, so the system clock can be re-configured. The

port returns not transparent 3-4TCL after the internal RSTF signal becomes high.

The same behavior just described, occurs also when unidirectional reset is selected and

RSTIN pin is held low till the end of the internal sequence (exactly 1024TCL + max 16 TCL)

and released exactly at that time.

Note:

When running with CPU frequency lower than 40 MHz, the minimum valid reset pulse to be

recognized by the CPU (4 TCL) could be longer than the minimum analog filter delay (50ns);

so it might happen that a short reset pulse is not filtered by the analog input filter, but on the

other hand it is not long enough to trigger a CPU reset (shorter than 4 TCL): this would

generate a FLASH reset but not a system reset. In this condition, the FLASH answers

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