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ST10F276Z5 数据表(PDF) 118 Page - STMicroelectronics |
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ST10F276Z5 数据表(HTML) 118 Page - STMicroelectronics |
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118 / 239 page  System reset ST10F276Z5 118/239 Figure 31. Synchronous long hardware RESET (EA = 0) 1. If during the reset condition (RSTIN low), RPD voltage drops below the threshold voltage (about 2.5 V for 5 V operation), the asynchronous reset is then immediately entered. 2. Minimum RSTIN low pulse duration shall also be longer than 500ns to guarantee the pulse is not masked by the internal filter (refer to Section 19.6). 3. 3. 3 to 8 TCL depending on clock source selection. P0[15:13] not transparent RSTF P0[12:2] transparent not t. P0[1:0] not t. not transparent RST 1024+8 TCL 3..8 TCL3) 1) V RPD > 2.5 V Asynchronous Reset not entered 200 µA Discharge RPD RSTOUT At this time RSTF is sampled LOW so it is LONG reset (After Filter) RSTIN 1024+8 TCL 4 TCL2) 12 TCL ≤ 500 ns ≥ 50 ns ≤ 500 ns ≥ 50 ns ≤ 500 ns ≥ 50 ns ALE 8 TCL not t. transparent 3..4 TCL |
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