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ST10F276Z5 数据表(PDF) 122 Page - STMicroelectronics |
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ST10F276Z5 数据表(HTML) 122 Page - STMicroelectronics |
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122 / 239 page  System reset ST10F276Z5 122/239 internal signal RSTF) is sufficiently held low by the external hardware to inject a Long Hardware reset. After this occurrence, the initialization routine is not able to recognize a Software or Watchdog bidirectional reset event, since a different source is flagged inside WDTCON register. This phenomenon does not occur when internal FLASH is selected during reset (EA = 1), since the initialization of the FLASH itself extend the internal reset duration well beyond the filter delay. Next Figure 34, Figure 35 and Figure 36 summarize the timing for Software and Watchdog Timer Bidirectional reset events: In particular Figure 36 shows the degeneration into Hardware reset. Figure 34. SW / WDT bidirectional RESET (EA=1) P0[15:13] not transparent RSTF P0[12:8] transparent not t. P0[1:0] not t. not transparent RST 1024 TCL RSTOUT (After Filter) RSTIN ≤ 500 ns ≥ 50 ns ≤ 500 ns ≥ 50 ns IBUS-CS 7 TCL FLARST ≤ 1 ms ≤ 2 TCL (Internal) P0[7:2] not transparent |
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