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ST10F276Z5 数据表(PDF) 170 Page - STMicroelectronics |
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ST10F276Z5 数据表(HTML) 170 Page - STMicroelectronics |
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170 / 239 page  Register set ST10F276Z5 170/239 WRCFG Write configuration control (inverted copy of WRC bit of RP0H) ‘0’: Pins WR and BHE retain their normal function. ‘1’: Pin WR acts as WRL, pin BHE acts as WRH. CLKEN System clock output enable (CLKOUT) ‘0’: CLKOUT disabled, pin may be used for general purpose I/O. ‘1’: CLKOUT enabled, pin outputs the system clock signal or a prescaled value of system clock according to XCLKOUTDIV register setting. BYTDIS Disable/enable control for pin BHE (set according to data bus width) ‘0’: Pin BHE enabled. ‘1’: Pin BHE disabled, pin may be used for general purpose I/O. ROMEN Internal memory enable (set according to pin EA during reset) ‘0’: Internal memory disabled: Accesses to the IFlash Memory area use the external bus. ‘1’: Internal memory enabled. SGTDIS Segmentation disable/enable control ‘0’: Segmentation enabled (CSP is saved/restored during interrupt entry/exit). ‘1’: Segmentation disabled (Only IP is saved/restored). ROMS1 Internal memory mapping ‘0’: Internal memory area mapped to segment 0 (00’0000h...00’7FFFh). ‘1’: Internal memory area mapped to segment 1 (01’0000h...01’7FFFh). STKSZ System stack size Selects the size of the system stack (in the internal I-RAM) from 32 to 1024 words. BUSCON0 (FF0Ch / 86h) SFR Reset value: 0xx0h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CSWEN0 CSREN0 RDYPOL0 RDYEN0 - BUSACT0 ALECTL0 - BTYP MTTC0 RWDC0 MCTC RW RW RW RW RW RW RW RW RW BUSCON1 (FF14h / 8Ah) SFR Reset value: 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CSWEN1 CSREN1 RDYPOL1 RDYEN1 - BUSACT1 ALECTL1 - BTYP MTTC1 RWDC1 MCTC RW RW RW RW RW RW RW RW RW RW BUSCON2 (FF16h / 8Bh) SFR Reset value: 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CSWEN2 CSREN2 RDYPOL2 RDYEN2 - BUSACT2 ALECTL2 - BTYP MTTC2 RWDC2 MCTC RW RW RW RW RW RW RW RW RW BUSCON3 (FF18h / 8Ch) SFR Reset value: 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CSWEN3 CSREN3 RDYPOL3 RDYEN3 - BUSACT3 ALECTL3 - BTYP MTTC3 RWDC3 MCTC RW RW RW RW RW RW RW RW RW Table 79. SYSCON description (continued) Bit Function |
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