MPC8343ECVRADDB datasheet(64/79 Pages) FREESCALE

64 / 79 page

MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 10

Freescale Semiconductor

Clocking

19.2

Core PLL Configuration

RCWL[COREPLL] selects the ratio between the internal coherent system bus clock (csb_clk) and the e300

core clock (core_clk). Table 57 shows the encodings for RCWL[COREPLL]. COREPLL values that are

not listed in Table 57 should be considered as reserved.

NOTE

Core VCO frequency = core frequency

× VCO divider

VCO divider must be set properly so that the core VCO frequency is in the

range of 800–1800 MHz.

High

0011

6 : 1

100

150

200

High

0100

8 : 1

133

200

266

High

0101

10 : 1

166

250

333

High

0110

12 : 1

200

300

High

0111

14 : 1

233

High

1000

16 : 1

266

1 CFG_CLKIN_DIV doubles csb_clk if set high.

2 CLKIN is the input clock in host mode; PCI_CLK is the input clock in agent mode.

DDR2 memory may be used at 133 MHz provided that the memory components are specified for operation at this frequency.

Table 57. e300 Core PLL Configuration

RCWL[COREPLL]

core_clk : csb_clk Ratio

VCO Divider1

0–1

2–5

0000

PLL bypassed

(PLL off, csb_clk clocks core directly)

PLL bypassed

(PLL off, csb_clk clocks core directly)

0001

01:1

0001

01:1

0001

01:1

0001

01:1

0001

1.5:1

0001

1.5:1

0001

1.5:1

0001

1.5:1

Table 56. CSB Frequency Options for Agent Mode (continued)

CFG_CLKIN_DIV

at Reset1

SPMF

csb_clk :

Input Clock Ratio2

Input Clock Frequency (MHz)2

16.67

33.33

66.67

csb_clk Frequency (MHz)

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