MPC8343ECVRADDB datasheet(12/79 Pages) FREESCALE

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MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 10

Freescale Semiconductor

RESET Initialization

4.3

TSEC Gigabit Reference Clock Timing

Table 8 provides the TSEC gigabit reference clocks (EC_GTX_CLK125) AC timing specifications.

RESET Initialization

This section describes the DC and AC electrical specifications for the reset initialization timing and

electrical requirements of the MPC8343EA.

CLKIN/PCI_CLK duty cycle

tKHK/tCLKIN

—

CLKIN/PCI_CLK jitter

—

±150

4, 5

Notes:

1. Caution: The system, core, USB, security, and TSEC must not exceed their respective maximum or minimum operating

frequencies.

2. Rise and fall times for CLKIN/PCI_CLK are measured at 0.4 and 2.7 V.

3. Timing is guaranteed by design and characterization.

4. This represents the total input jitter—short term and long term—and is guaranteed by design.

5. The CLKIN/PCI_CLK driver’s closed loop jitter bandwidth should be < 500 kHz at –20 dB. The bandwidth must be set low to

allow cascade-connected PLL-based devices to track CLKIN drivers with the specified jitter.

6. Spread spectrum clocking is allowed with 1% input frequency down-spread at maximum 50 KHz modulation rate regardless

of input frequency.

Table 8. EC_GTX_CLK125 AC Timing Specifications

At recommended operating conditions with LVDD = 2.5 ± 0.125 mV/ 3.3 V ± 165 mV

Parameter

Symbol

Min

Typical

Max

Unit

Notes

EC_GTX_CLK125 frequency

tG125

—125

—

MHz

—

EC_GTX_CLK125 cycle time

tG125

—8

—

EC_GTX_CLK rise and fall time

LVDD = 2.5 V

LVDD = 3.3 V

tG125R/tG125F

——

0.75

1.0

EC_GTX_CLK125 duty cycle

GMII, TBI

1000Base-T for RGMII, RTBI

tG125H/tG125

—

EC_GTX_CLK125 jitter

—

±150

Notes:

1. Rise and fall times for EC_GTX_CLK125 are measured from 0.5 and 2.0 V for LVDD = 2.5 V and from 0.6 and 2.7 V for

LVDD =3.3 V.

2. EC_GTX_CLK125 is used to generate the GTX clock for the eTSEC transmitter with 2% degradation. The EC_GTX_CLK125

duty cycle can be loosened from 47%/53% as long as the PHY device can tolerate the duty cycle generated by the eTSEC

GTX_CLK. See Section 8.2.2, “RGMII and RTBI AC Timing Specifications for the duty cycle for 10Base-T and 100Base-T

reference clock.

Table 7. CLKIN AC

Timing Specifications (continued)

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