MPC8343VRAGDB datasheet(29/79 Pages) FREESCALE

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MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 10

Freescale Semiconductor

USB

9USB

This section provides the AC and DC electrical specifications for the USB interface of the MPC8343EA.

9.1

USB DC Electrical Characteristics

Table 31 provides the DC electrical characteristics for the USB interface.

9.2

USB AC Electrical Specifications

Table 32 describes the general timing parameters of the USB interface of the MPC8343EA.

Table 31. USB DC Electrical Characteristics

Parameter

Symbol

Min

Max

Unit

High-level input voltage

VIH

2OVDD +0.3

Low-level input voltage

VIL

–0.3

0.8

Input current

IIN

—±5

μA

High-level output voltage, IOH = –100 μAVOH

OVDD –0.2

—

Low-level output voltage, IOL = 100 μAVOL

—0.2

Table 32. USB General Timing Parameters (ULPI Mode Only)

Parameter

Symbol1

Min

Max

Unit

Notes

USB clock cycle time

tUSCK

—

2–5

Input setup to USB clock—all inputs

tUSIVKH

—

2–5

Input hold to USB clock—all inputs

tUSIXKH

—

2–5

USB clock to output valid—all outputs

tUSKHOV

—

2–5

Output hold from USB clock—all outputs

tUSKHOX

—

2–5

Notes:

1. The symbols for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for inputs

and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tUSIXKH symbolizes USB timing (US) for

the input (I) to go invalid (X) with respect to the time the USB clock reference (K) goes high (H). Also, tUSKHOX symbolizes

USB timing (US) for the USB clock reference (K) to go high (H), with respect to the output (O) going invalid (X) or output hold

time.

2. All timings are in reference to USB clock.

3. All signals are measured from OVDD/2 of the rising edge of the USB clock to 0.4 × OVDD of the signal in question for 3.3 V

signaling levels.

4. Input timings are measured at the pin.

5. For active/float timing measurements, the Hi-Z or off-state is defined to be when the total current delivered through the

component pin is less than or equal to that of the leakage current specification.

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