MPC8343VRAGDB datasheet(5/79 Pages) FREESCALE

5 / 79 page

MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 10

Freescale Semiconductor

Overview

— Can operate as a stand-alone USB host controller

– USB root hub with one downstream-facing port

– Enhanced host controller interface (EHCI) compatible

– High-speed (480 Mbps), full-speed (12 Mbps), and low-speed (1.5 Mbps) operations

— External PHY with UTMI, serial and UTMI+ low-pin interface (ULPI)

•

Local bus controller (LBC)

— Multiplexed 32-bit address and data operating at up to 133 MHz

— Eight chip selects for eight external slaves

— Up to eight-beat burst transfers

— 32-, 16-, and 8-bit port sizes controlled by an on-chip memory controller

— Three protocol engines on a per chip select basis:

– General-purpose chip select machine (GPCM)

– Three user-programmable machines (UPMs)

– Dedicated single data rate SDRAM controller

— Parity support

— Default boot ROM chip select with configurable bus width (8-, 16-, or 32-bit)

•

Programmable interrupt controller (PIC)

— Functional and programming compatibility with the MPC8260 interrupt controller

— Support for 8 external and 35 internal discrete interrupt sources

— Support for 1 external (optional) and 7 internal machine checkstop interrupt sources

— Programmable highest priority request

— Four groups of interrupts with programmable priority

— External and internal interrupts directed to host processor

— Redirects interrupts to external INTA pin in core disable mode.

— Unique vector number for each interrupt source

•

Dual industry-standard I2C interfaces

— Two-wire interface

— Multiple master support

— Master or slave I2C mode support

— On-chip digital filtering rejects spikes on the bus

— System initialization data optionally loaded from I2C-1 EPROM by boot sequencer embedded

hardware

•

DMA controller

— Four independent virtual channels

— Concurrent execution across multiple channels with programmable bandwidth control

— Handshaking (external control) signals for all channels: DMA_DREQ[0:3],

DMA_DACK[0:3], DMA_DDONE[0:3]

— All channels accessible to local core and remote PCI masters

MPC8343VRAGDB 数据表(PDF) 5 Page - Freescale Semiconductor, Inc

MPC8343VRAGDB 数据表(HTML) 5 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79

数据表下载