MPC8343VRAGDB datasheet(9/79 Pages) FREESCALE

9 / 79 page

MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 10

Freescale Semiconductor

Electrical Characteristics

Figure 3 shows the undershoot and overshoot voltage of the PCI interface of the MPC8343EA for the

3.3-V signals, respectively.

Figure 3. Maximum AC Waveforms on PCI Interface for 3.3-V Signaling

2.1.3

Output Driver Characteristics

Table 3 provides information on the characteristics of the output driver strengths. The values are

preliminary estimates.

2.2

Power Sequencing

The device does not require the core supply voltage and I/O supply voltages to be applied in any particular

order. Note that during the power ramp up, before the power supplies are stable, there may be a period of

time that I/O pins are actively driven. After the power is stable, as long as PORESET is asserted, most I/O

pins are three-stated. To minimize the time that I/O pins are actively driven, it is recommended to apply

core voltage before I/O voltage and assert PORESET before the power supplies fully ramp up.

Table 3. Output Drive Capability

Driver Type

Output Impedance

(

Ω)

Supply

Voltage

Local bus interface utilities signals

OVDD = 3.3 V

PCI signals (not including PCI output clocks)

PCI output clocks (including PCI_SYNC_OUT)

DDR signal

GVDD = 2.5 V

DDR2 signal

36 (half strength mode)

GVDD = 1.8 V

TSEC/10/100 signals

LVDD = 2.5/3.3 V

DUART, system control, I2C, JTAG, USB

OVDD = 3.3 V

GPIO signals

OVDD = 3.3 V,

LVDD = 2.5/3.3 V

Undervoltage

Waveform

Overvoltage

Waveform

11 ns

(Min)

+7.1 V

7.1 V p-to-p

(Min)

4 ns

(Max)

–3.5 V

7.1 V p-to-p

(Min)

62.5 ns

+3.6 V

0 V

4 ns

(Max)

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