MPC8343VRAGDB datasheet(67/79 Pages) FREESCALE

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MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 10

Freescale Semiconductor

Thermal

20 Thermal

This section describes the thermal specifications of the MPC8343EA.

20.1

Thermal Characteristics

.Table 59 provides the package thermal characteristics for the 620 29

× 29 mm PBGA of the MPC8343EA.

20.2

Thermal Management Information

For the following sections, PD = (VDD × IDD) + PI/O where PI/O is the power dissipation of the I/O drivers.

See Table 5 for I/O power dissipation values.

20.2.1

Estimation of Junction Temperature with Junction-to-Ambient

Thermal Resistance

An estimation of the chip junction temperature, TJ, can be obtained from the equation:

TJ = TA + (RθJA × PD)

where:

TJ = junction temperature (°C)

TA = ambient temperature for the package (°C)

RθJA = junction-to-ambient thermal resistance (°C/W)

PD = power dissipation in the package (W)

Table 59. Package Thermal Characteristics for PBGA

Parameter

Symbol

Value

Unit

Notes

Junction-to-ambient natural convection on single-layer board (1s)

RθJA

°C/W

1, 2

Junction-to-ambient natural convection on four-layer board (2s2p)

RθJMA

°C/W

1, 3

Junction-to-ambient (at 200 ft/min) on single-layer board (1s)

RθJMA

°C/W

1, 3

Junction-to-ambient (at 200 ft/min) on four-layer board (2s2p)

RθJMA

°C/W

1, 3

Junction-to-board thermal

RθJB

°C/W

Junction-to-case thermal

RθJC

°C/W

Junction-to-package natural convection on top

°C/W

Notes

1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board)

temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal

resistance.

2. Per SEMI G38-87 and JEDEC JESD51-2 with the single-layer board horizontal.

3. Per JEDEC JESD51-6 with the board horizontal.

4. Thermal resistance between the die and the printed-circuit board per JEDEC JESD51-8. Board temperature is measured on

the top surface of the board near the package.

5. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method

1012.1).

6. Thermal characterization parameter indicating the temperature difference between package top and the junction temperature

per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT.

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