MPC8343VRAGDB datasheet(11/79 Pages) FREESCALE

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MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 10

Freescale Semiconductor

Clock Input Timing

This section provides the clock input DC and AC electrical characteristics for the device.

4.1

DC Electrical Characteristics

Table 6 provides the clock input (CLKIN/PCI_SYNC_IN) DC timing specifications for the MPC8343EA.

4.2

AC Electrical Characteristics

The primary clock source for the MPC8343EA can be one of two inputs, CLKIN or PCI_CLK, depending

on whether the device is configured in PCI host or PCI agent mode. Table 7 provides the clock input

(CLKIN/PCI_CLK) AC timing specifications for the device.

TSEC I/O

load = 25 pF

MII

—

0.01

—

Multiply by number

of interfaces used.

GMII or TBI

—

0.06

—

RGMII or RTBI

—

0.04

USB

12 MHz

—

0.01

—

480 MHz

—

0.2

—

Other I/O

—

0.01

—

Table 6. CLKIN DC Timing Specifications

Parameter

Condition

Symbol

Min

Max

Unit

Input high voltage

—

VIH

2.7

OVDD +0.3

Input low voltage

—

VIL

–0.3

0.4

CLKIN input current

0 V

≤ V

IN ≤ OVDD

IIN

—

±10

μA

PCI_SYNC_IN input current

0 V

≤ V

IN ≤ 0.5 V or

OVDD –0.5 V ≤ VIN ≤ OVDD

IIN

—

±10

μA

PCI_SYNC_IN input current

0.5 V

≤V

IN ≤ OVDD – 0.5 V

IIN

—

±50

μA

Table 7. CLKIN AC

Timing Specifications

Parameter/Condition

Symbol

Min

Typical

Max

Unit

Notes

CLKIN/PCI_CLK frequency

fCLKIN

——

MHz

1, 6

CLKIN/PCI_CLK cycle time

tCLKIN

—

CLKIN/PCI_CLK rise and fall time

tKH, tKL

0.6

1.0

2.3

Table 5. MPC8343EA Typical I/O Power Dissipation (continued)

Interface

Parameter

DDR2

GVDD

(1.8 V)

DDR1

GVDD

(2.5 V)

OVDD

(3.3 V)

LVDD

(3.3 V)

LVDD

(2.5 V)

Unit

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