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MPC8572ECVTATLD 数据表(PDF) 40 Page - Freescale Semiconductor, Inc |
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MPC8572ECVTATLD 数据表(HTML) 40 Page - Freescale Semiconductor, Inc |
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40 / 140 page ![]() MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4 40 Freescale Semiconductor Ethernet: Enhanced Three-Speed Ethernet (eTSEC) Figure 18 shows the RGMII and RTBI AC timing and multiplexing diagrams. Figure 18. RGMII and RTBI AC Timing and Multiplexing Diagrams 8.2.7 RMII AC Timing Specifications This section describes the RMII transmit and receive AC timing specifications. 8.2.7.1 RMII Transmit AC Timing Specifications Table 34 shows the RMII transmit AC timing specifications. Table 34. RMII Transmit AC Timing Specifications At recommended operating conditions with LVDD/TVDD of 2.5/ 3.3 V ± 5%. Parameter/Condition Symbol 1 Min Typ Max Unit TSECn_TX_CLK clock period tRMT 15.0 20.0 25.0 ns TSECn_TX_CLK duty cycle tRMTH 35 50 65 % TSECn_TX_CLK peak-to-peak jitter tRMTJ — — 250 ps Rise time TSECn_TX_CLK (20%–80%) tRMTR 1.0 — 2.0 ns Fall time TSECn_TX_CLK (80%–20%) tRMTF 1.0 — 2.0 ns GTX_CLK tRGT tRGTH tSKRGT TX_CTL TXD[8:5] TXD[7:4] TXD[9] TXERR TXD[4] TXEN TXD[3:0] (At Transmitter) TXD[8:5][3:0] TXD[7:4][3:0] TX_CLK (At PHY) RX_CTL RXD[8:5] RXD[7:4] RXD[9] RXERR RXD[4] RXDV RXD[3:0] RXD[8:5][3:0] RXD[7:4][3:0] RX_CLK (At PHY) tSKRGT tSKRGT tSKRGT |
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