MPC8572ECVTATLD datasheet(15/140 Pages) FREESCALE

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MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4

Freescale Semiconductor

Power Characteristics

NOTE

From a system standpoint, if any of the I/O power supplies ramp prior to the

VDD core supply, the I/Os associated with that I/O supply may drive a logic

one or zero during power-on reset, and extra current may be drawn by the

device.

Power Characteristics

The estimated typical power dissipation for the core complex bus (CCB) versus the core frequency for this

family of PowerQUICC III devices is shown in Table 4.

Input Clocks

4.1

System Clock Timing

Table 5 provides the system clock (SYSCLK) AC timing specifications for the MPC8572E.

Table 4. MPC8572E Power Dissipation 1

1 This reflects the MPC8572E power dissipation excluding the power dissipation from B/G/L/O/T/XV

DD rails.

CCB Frequency

Core Frequency

Typical-652

2 Typical-65 is based on V

DD = 1.1 V, Tj = 65 °C, running Dhrystone.

Typical-1053

3 Typical-105 is based on V

DD = 1.1 V, Tj = 105 °C, running Dhrystone.

Maximum4

4 Maximum is based on V

DD = 1.1 V, Tj = 105 °C, running a smoke test.

Unit

533

1067

12.3

17.8

18.5

533

1200

12.3

17.8

18.5

533

1333

16.3

22.8

24.5

600

1500

17.3

23.9

25.9

Notes:

Table 5. SYSCLK AC Timing Specifications

At recommended operating conditions with OVDD of 3.3V ± 5%.

Parameter/Condition

Symbol

Min

Typical

Max

Unit

Notes

SYSCLK frequency

fSYSCLK

—

133

MHz

SYSCLK cycle time

tSYSCLK

7.5

—

30.3

—

SYSCLK rise and fall time

tKH, tKL

0.61.0

1.2ns

SYSCLK duty cycle

tKHK/tSYSCLK

—

MPC8572ECVTATLD 数据表(PDF) 15 Page - Freescale Semiconductor, Inc

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