MPC8572ECVTATLD datasheet(82/140 Pages) FREESCALE

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MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4

Freescale Semiconductor

PCI Express

•

Section 16, “PCI Express”

•

Section 17, “Serial RapidIO”

Note that external AC Coupling capacitor is required for the above three serial transmission protocols with

the capacitor value defined in specification of each protocol section.

16 PCI Express

This section describes the DC and AC electrical specifications for the PCI Express bus of the MPC8572E.

16.1

DC Requirements for PCI Express SD1_REF_CLK and

SD1_REF_CLK

For more information, see Section 15.2, “SerDes Reference Clocks.”

16.2

AC Requirements for PCI Express SerDes Reference Clocks

Table 60 lists AC requirements.

16.3

Clocking Dependencies

The ports on the two ends of a link must transmit data at a rate that is within 600 parts per million (ppm)

of each other at all times. This is specified to allow bit rate clock sources with a +/– 300 ppm tolerance.

16.4

Physical Layer Specifications

The following is a summary of the specifications for the physical layer of PCI Express on this device. For

further details as well as the specifications of the transport and data link layer, Use the PCI Express Base

Specification. REV. 1.0a document.

16.4.1

Differential Transmitter (TX) Output

Table 61 defines the specifications for the differential output at all transmitters (TXs). The parameters are

specified at the component pins.

Table 60. SD1_REF_CLK and SD1_REF_CLK AC Requirements

Symbol

Parameter Description

Min

Typical

Max

Units

Notes

tREF

REFCLK cycle time

—

tREFCJ

REFCLK cycle-to-cycle jitter. Difference in the period of any two adjacent

REFCLK cycles

—

100

—

tREFPJ

Phase jitter. Deviation in edge location with respect to mean edge location

–50

—

Notes:

1. Typical cycle time is based on PCI Express Card Electromechanical Specification Revision 1.0a.

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