Sensors

Freescale Semiconductor

25

MMA690xQ

SECTION 4 OPERATING MODES

MMA690xQ operates in one of two modes, factory test programming mode and normal operating mode. Factory test and pro-

gramming mode is entered only when certain conditions are met, and provides support for programming of customer-defined

data. Normal mode is entered by default when the device is powered on.

4.1

NORMAL OPERATING MODE

acceleration data and device support data transfers are supported.

4.1.1

Power-On Reset

ternal reset signal is asserted at this time. Separate comparators on monitor all three voltages, and when all are above specified

thresholds, the reset signal is negated and the device begins its initialization process.

4.1.2

Device Initialization

Following any reset, the device completes a sequence of operations which initialize internal circuitry. Device initialization is

completed in two phases. During the first phase, the fuse array is read and its contents are transferred to mirror registers. Power

to the fuse array is then removed to reduce supply current load. A voltage reference used within the sensor interface stabilizes

during the second phase. If the HPFSEL bit is set in the DSP configuration register (DSPCFG), the high-pass filter is also initial-

ized during phase two.

The device will not respond to SPI accesses during initialization phase one. Acceleration results are not available during ini-

tialization phase two, however the SPI is functional and register operations may be performed. If an acceleration data access is

attempted, the device will respond with non-acceleration data. The specific response depends upon the Communications Proto-

col selected.

The first initialization phase requires approximately 800

μs to complete. The second phase completes in approximately 3.0 ms

if no high-pass filter is selected, and 200 ms if the HPFSEL bit is programmed to a logic ‘1’ state. The DEVINIT bit in the device

status register (DEVSTAT) remains set following reset until the second phase of device initialization completes.

Following completion of the device initialization, the DEVRES bit in DEVSTAT may be cleared by writing a logic ‘1’ value to CE

in DEVCTL. This operation will clear the device reset exception. Once cleared, register operations may be completed or accel-

eration data values may be read from the device in any desired sequence.