Sensors

Freescale Semiconductor

9

MMA690xQ

2.1.3.2

Clear Error (CE)

Setting this bit to a logic ‘1’ state will clear transient error status conditions. It is necessary to either set this bit or perform a

device reset if an error condition has been reported by the device before acceleration data transfer can be resumed. The device

reset condition may be cleared only after device initialization has completed.

Error conditions and classification are described in Section 3.1.

The state of this bit is always read as logic ‘0’.

2.1.3.3

PCM Enable (PCM_EN)

This bit controls the PCM_X and PCM_Y outputs along with internal circuitry which generates a pulse-code modulated signal

from the acceleration result. When this bit is set, the PCM outputs are enabled. When cleared, PCM_X and PCM_Y are driven

to a logic low level.

2.1.3.4

High-pass Filter Bypass (HPFB)

The high-pass filter is disabled through factory settings, therefore writing this bit will have no effect. If read, this bit will be “0”.

2.1.3.5

Y-Axis Signal Inversion Control (YINV)

This control function is provided as a means to verify operation of the two-channel multiplexor which alternately provides

X-axis and Y-axis data to the DSP. An inverter block and multiplexor at the Y-axis input to the DSP are controlled by the YINV bit.

Setting this bit when ST0 is set has the effect of changing the sign of acceleration in the Y-axis. Operation of the YINV bit is

illustrated in Figure 2-1. Y-axis inversion may be selected only during self-test; the state of this bit has no effect when ST0 is

cleared.

Figure 2-1 Y-Axis Inversion Function

Self-test operations controlled by YINV along with ST1 and ST0 are summarized in the Table 2-5.

2.1.3.6

Self-test Control (ST1, ST0)

Bidirectional self-test control is provided through manipulation of these bits. ST1 controls direction while ST0 enables and dis-

ables the self-test circuitry. ST1 and ST0 are always cleared following internal reset. When ST0 is set, the high-pass filter is by-

passed and the values within the high-pass filter are frozen. Both axes are affected simultaneously by the state of these bits. If

the offset monitor is enabled, self-test activation in a single direction should be limited to less than 30 ms.

Communications Protocol bits S2 - S1 are inverted when self-test is activated, as described in Section 3.2.

Offset correction is applied within the DSP, and is not affected by the state of the YINV bit. Consequently, inversion of the

Y-axis signal may result in saturation of the Y-axis output value.

Correct operation of the DSP input multiplexor may be confirmed by performing the operations shown in Figure 2-2.

Table 2-5. Self-Test Control Operations

YINV

ST1

ST0

Self-Test Operation

X-Axis

Y-Axis

X

X

0

Self-test Disabled, Y-Axis Signal Inversion Disabled

0

0

1

Positive Deflection

0

1

1

Negative Deflection

1

0

1

Positive Deflection

Negative Deflection

1

1

1

Negative Deflection

Positive Deflection

DSP

YINV

ΣΔ

CONVERTER

SINC

FILTER

X-AXIS

ΣΔ

CONVERTER

Y-AXIS

SINC

FILTER

ST0

0

1