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Freescale Semiconductor

17

MMA690xQ

SECTION 3 SERIAL COMMUNICATIONS

Digital data communication is completed through synchronous serial transfers via the SPI port. Conventional SPI protocol is

employed, acting as a slave device observing CPOL = 0, CPHA = 0, MSB first. A number of data integrity features are incorpo-

rated into the transfer protocols.

3.1

EXCEPTION CONDITIONS

Under certain conditions, the MMA690xQ will respond to serial commands with a word, which indicates that an exception con-

dition has been detected. Response varies according to the Communication Protocol selected. Exceptions fall into five classes

and are prioritized. If multiple exception conditions are detected, only the exception of highest priority is reported.

A reset exception condition exists following any device reset. Immediately following reset, a Device Initialization condition will

be indicated until internal initialization of the circuitry has completed. Following internal initialization, a Device Reset exception

condition exists until explicitly cleared by writing a logic ‘1’ to the CE bit in DEVCTL.

Transient exception conditions result from data transmission errors such as data parity faults, an invalid number of clock

cycles, etc. These exceptions are indicated during the following SPI transfer operation. These exceptions do not require an ex-

plicit operation to be cleared.

Behavioral exception conditions are defined as those which affect acceleration data results but do not indicate an error condi-

tion. In MMA690xQ, the two behavioral exceptions are activation of self-test and a hold condition resulting from the external CAP/

HOLD pin being driven to a logic high state. Register operations are unaffected by behavioral exceptions. Acceleration data trans-

fers will complete, with the S/T1 and S/T0 bits indicating that one or both behavioral exception conditions exist.

See Section 3.2 for behavioral exceptions reported by the Communications Protocol.

Critical error exceptions exist when an internal fault, which affects the reliability of device operation or acceleration results, is

detected. If a critical error condition exists, an invalid data value is produced by the device in lieu of acceleration results. Register

operations are unaffected except for the state of S[2:0]. Some critical errors, such as Temperature Fault, may be cleared by

writing a logic ‘1’ to the CE bit in DEVCTL, provided the underlying fault condition no longer persists. Other critical error conditions

require reset of the device to clear.

3.1.1

Defined Exceptions

3.1.1.1

Internal Data Error

Class: Critical error

During reset, a number of internal registers are loaded from a fuse array which stores factory-programmed values. The resis-

tance of each fuse is measured and compared to thresholds to ensure integrity of programmed data. Additionally, the register

array is continuously monitored for correct parity at all time while the device is powered. If either the margin test or parity verifi-

cation fail, an internal data error exception is reported.

Device reset is required to clear this exception condition.

3.1.1.2

Internal Oscillator Fault

Class: Critical error

Device reset is required to clear this exception condition.

Figure 3-1 Oscillator Failure Response

SCLK

CS