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MMA6901K 数据表(PDF) 20 Page - Freescale Semiconductor, Inc |
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MMA6901K 数据表(HTML) 20 Page - Freescale Semiconductor, Inc |
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20 / 36 page  Sensors 20 Freescale Semiconductor MMA690xQ ST = Self-test active Commands and response under normal and exception conditions are summarized in the following tables. Note that only DEVCTL at address $0E is writable when the device is in its normal operating mode. P: Parity T[1:0] Transfer type code Note that only DEVCTL is writable when the device operates in normal operating mode. Attempts to write other registers do not constitute a fault condition, but have no effect. P: Parity T[1:0] Transfer type code Table 3-3. Device Response, Exception Conditions Exception Command Response Priority Class ST HOLD T1 T0 S2 S1 S0 Register Acceleration Data Transient X X X X 1 1 1 Status code Status code Highest Reset X X T1 T0 1 1 1 As requested $7FF ² Critical X X 1 1 1 ² Behavioral 1 1 0 T1 T0 As requested ² 1 0 1 T1 T0 ² 0 1 1 T1 T0 ² None 0 0 0 T1 T0 Lowest Table 3-4. Normal Response Summary Operation Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Acceleration Data Read Command T1 T0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Response 0 T1 T0 P D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 Register Pointer Read Command 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 Response 0 0 0 0 0 P 0 0 A7 A6 A5 A4 A3 A2 A1 A0 Register Pointer Write Command 0 0 0 1 0 P 0 0 A7 A6 A5 A4 A3 A2 A1 A0 Response 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 Register Data Read Command 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 Response 0 0 0 1 0 P 0 0 D7 D6 D5 D4 D3 D2 D1 D0 Register Data Write Command 0 0 1 1 0 P 0 0 D7 D6 D5 D4 D3 D2 D1 D0 Response 0 0 0 1 1 P 0 0 A7 A6 A5 A4 A3 A2 A1 A0 Table 3-5. Behavioral Response Summary, One Exception Condition Operation Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Acceleration Data Read Command T1 T0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Response 1 T1 T0 P D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 Register Pointer Read Command 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 Response 1 1 1 0 0 P 0 1 A7 A6 A5 A4 A3 A2 A1 A0 Register Pointer Write Command 0 0 0 1 0 P 0 0 A7 A6 A5 A4 A3 A2 A1 A0 Response 1 1 1 0 1 0 0 1 0 0 0 0 0 0 0 0 Register Data Read Command 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 Response 1 1 1 1 0 P 0 1 D7 D6 D5 D4 D3 D2 D1 D0 Register Data Write Command 0 0 1 1 0 P 0 0 D7 D6 D5 D4 D3 D2 D1 D0 Response 1 1 1 1 1 P 0 1 A7 A6 A5 A4 A3 A2 A1 A0 |
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