HT68FU50 datasheet(54/244 Pages) HOLTEK

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HT68F20/HT68F30/HT68F40/HT68F50/HT68F60

HT68FU30/HT68FU40/HT68FU50/HT68FU60

Rev. 1.50

March 15, 2011

Pulling the RES Pin low using external hardware will

also execute a device reset. In this case, as in the

case of other resets, the Program Counter will reset to

zero and program execution initiated from this point.

· Low Voltage Reset

- LVR

The microcontroller contains a low voltage reset circuit

in order to monitor the supply voltage of the device,

which is selected via a configuration option. If the supply

voltage of the device drops to within a range of

0.9V~VLVR such as might occur when changing the bat-

tery, the LVR will automatically reset the device inter-

nally. The LVR includes the following specifications: For

a valid LVR signal, a low voltage, i.e., a voltage in the

range between 0.9V~VLVR must exist for greater than

the value tLVR specified in the A.C. characteristics. If the

low voltage state does not exceed tLVR, the LVR will ig-

nore it and will not perform a reset function. One of a

range of specified voltage values for VLVR can be se-

lected using configuration options.

· Watchdog Time-out Reset during Normal Operation

The Watchdog time-out Reset during normal opera-

tion is the same as a hardware RES pin reset except

that the Watchdog time-out flag TO will be set to

²1².

· Watchdog Time-out Reset during SLEEP or IDLE

Mode

The Watchdog time-out Reset during SLEEP or IDLE

Mode is a little different from other kinds of reset. Most

of the conditions remain unchanged except that the

Program Counter and the Stack Pointer will be

cleared to

²0² and the TO flag will be set to ²1². Refer

to the A.C. Characteristics for tSST details.

Note:

The tSST is 15~16 clock cycles if the system

clock source is provided by ERC or HIRC. The

tSST is 1024 clock for HXT or LXT. The tSST is

1~2 clock for LIRC.

Reset Initial Conditions

The different types of reset described affect the reset

flags in different ways. These flags, known as PDF and

TO are located in the status register and are controlled

by various microcontroller operations, such as the

SLEEP or IDLE Mode function or Watchdog Timer. The

reset flags are shown in the table:

TO PDF

RESET Conditions

Power-on reset

RES or LVR reset during NORMAL or

SLOW Mode operation

WDT time-out reset during NORMAL or

SLOW Mode operation

WDT time-out reset during IDLE or SLEEP

Mode operation

Note:

²u² stands for unchanged

The following table indicates the way in which the vari-

ous components of the microcontroller are affected after

a power-on reset occurs.

Item

Condition After RESET

Program Counter

Reset to zero

Interrupts

All interrupts will be disabled

WDT

Clear after reset, WDT begins

counting

Timer/Event

Counter

Timer Counter will be turned off

Input/Output Ports

I/O ports will be setup as inputs.

Stack Pointer

Stack Pointer will point to the top

of the stack

t R S T D + t S S T

W D T T i m e - o u t

I n t e r n a l R e s e t

Note: tRSTD is power-on delay, typical time=100ms

WDT Time-out Reset during Normal Operation

Timing Chart

t S S T

W D T T i m e - o u t

I n t e r n a l R e s e t

WDT Time-out Reset during SLEEP or IDLE

Timing Chart

L V R

I n t e r n a l R e s e t

t R S T D + t S S T

Note: tRSTD is power-on delay, typical time=100ms

Low Voltage Reset Timing Chart

R E S

I n t e r n a l R e s e t

0 . 9 V D D

0 . 4 V D D

t R S T D + t S S T

Note: tRSTD is power-on delay, typical time=100ms

RES Reset Timing Chart

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